timing1.twx

Xilinx的培训教程的源码 virtex

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<twReport><twHead><twExecVer>Release 8.1.03i - Timing Analyzer I.27</twExecVer><twCopyright>Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.</twCopyright><twDesign>C:\XUP\Markets\PLDs\Workshops\courses\v81_fpga_flow\xupv2pro\labsolutions\verilog\lab3\time_const\loopback_map.ncd</twDesign><twPCF>C:\XUP\Markets\PLDs\Workshops\courses\v81_fpga_flow\xupv2pro\labsolutions\verilog\lab3\time_const\loopback.pcf</twPCF><twDevInfo arch="virtex2p"><twDevName>xc2vp30</twDevName><twSpeedGrade>-7</twSpeedGrade><twSpeedVer>PRODUCTION 1.92 2005-11-04</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twBody><twVerboseRpt><twConst twConstType="twPathConst"><twConstHead><twConstName>TS_clk = PERIOD TIMEGRP &quot;clk&quot; 10 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold></twConstHead></twConst><twConst twConstType="twPathConst"><twConstHead><twConstName>TS_instance_name_CLKFX_BUF = PERIOD TIMEGRP &quot;instance_name_CLKFX_BUF&quot; TS_clk /
        0.5 HIGH 50%;</twConstName><twItemCnt>8839</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twMinPer>5.272</twMinPer></twConstHead><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>14.728</twSlack><twSrc BELType="RAM">my_program/ram_1024_x_18.A</twSrc><twDest BELType="FF">transmit/buf_0/register_bit_3</twDest><twTotPathDel>5.272</twTotPathDel><twDelConst>20.000</twDelConst><twClkUncert>0.000</twClkUncert><twDetPath maxSiteLen="11"><twSrc BELType='RAM'>my_program/ram_1024_x_18.A</twSrc><twDest BELType='FF'>transmit/buf_0/register_bit_3</twDest><twLogLvls>8</twLogLvls><twSrcSite>RAMB16.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk50MHz</twSrcClk><twPathDel><twSite>RAMB16.DOA7</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">1.401</twDelInfo><twComp>my_program/ram_1024_x_18</twComp><twBEL>my_program/ram_1024_x_18.A</twBEL></twPathDel><twPathDel><twSite>SLICE.G4</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instruction&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.275</twDelInfo><twComp>my_kcpsm3/sy&lt;3&gt;</twComp><twBEL>my_kcpsm3/reg_loop_register_bit_4/DP</twBEL></twPathDel><twPathDel><twSite>SLICE.G3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>my_kcpsm3/sy&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.275</twDelInfo><twComp>N91</twComp><twBEL>my_kcpsm3/operand_select_mux_4</twBEL></twPathDel><twPathDel><twSite>SLICE.F1</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>port_id&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>N91</twComp><twBEL>Ker0_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE.G4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>N91</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.275</twDelInfo><twComp>write_to_uart</twComp><twBEL>Ker0</twBEL></twPathDel><twPathDel><twSite>SLICE.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>N01</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>write_to_uart</twComp><twBEL>write_to_uart1</twBEL></twPathDel><twPathDel><twSite>SLICE.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>write_to_uart</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>transmit/buf_0/valid_write</twComp><twBEL>transmit/buf_0/valid_lut</twBEL></twPathDel><twPathDel><twSite>SLICE.BX</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>transmit/buf_0/valid_write</twComp></twPathDel><twPathDel><twSite>SLICE.COUT</twSite><twDelType>Tbxcy</twDelType><twDelInfo twEdge="twRising">0.656</twDelInfo><twComp>transmit/buf_0/pointer&lt;0&gt;</twComp><twBEL>transmit/buf_0/count_muxcy_0</twBEL><twBEL>transmit/buf_0/count_muxcy_1</twBEL></twPathDel><twPathDel><twSite>SLICE.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>transmit/buf_0/count_carry&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tciny</twDelType><twDelInfo twEdge="twRising">0.728</twDelInfo><twComp>transmit/buf_0/pointer&lt;2&gt;</twComp><twBEL>transmit/buf_0/count_muxcy_2</twBEL><twBEL>transmit/buf_0/count_xor</twBEL></twPathDel><twPathDel><twSite>SLICE.DY</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>transmit/buf_0/next_count&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.CLK</twSite><twDelType>Tdyck</twDelType><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>transmit/buf_0/pointer&lt;2&gt;</twComp><twBEL>transmit/buf_0/register_bit_3</twBEL></twPathDel><twLogDel>4.372</twLogDel><twRouteDel>0.900</twRouteDel><twTotDel>5.272</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">clk50MHz</twDestClk><twPctLog>82.9</twPctLog><twPctRoute>17.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>14.728</twSlack><twSrc BELType="RAM">my_program/ram_1024_x_18.A</twSrc><twDest BELType="FF">transmit/buf_0/register_bit_3</twDest><twTotPathDel>5.272</twTotPathDel><twDelConst>20.000</twDelConst><twClkUncert>0.000</twClkUncert><twDetPath maxSiteLen="11"><twSrc BELType='RAM'>my_program/ram_1024_x_18.A</twSrc><twDest BELType='FF'>transmit/buf_0/register_bit_3</twDest><twLogLvls>8</twLogLvls><twSrcSite>RAMB16.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk50MHz</twSrcClk><twPathDel><twSite>RAMB16.DOA4</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">1.401</twDelInfo><twComp>my_program/ram_1024_x_18</twComp><twBEL>my_program/ram_1024_x_18.A</twBEL></twPathDel><twPathDel><twSite>SLICE.G1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instruction&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.275</twDelInfo><twComp>my_kcpsm3/sy&lt;3&gt;</twComp><twBEL>my_kcpsm3/reg_loop_register_bit_4/DP</twBEL></twPathDel><twPathDel><twSite>SLICE.G3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>my_kcpsm3/sy&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.275</twDelInfo><twComp>N91</twComp><twBEL>my_kcpsm3/operand_select_mux_4</twBEL></twPathDel><twPathDel><twSite>SLICE.F1</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>port_id&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>N91</twComp><twBEL>Ker0_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE.G4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>N91</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.275</twDelInfo><twComp>write_to_uart</twComp><twBEL>Ker0</twBEL></twPathDel><twPathDel><twSite>SLICE.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>N01</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>write_to_uart</twComp><twBEL>write_to_uart1</twBEL></twPathDel><twPathDel><twSite>SLICE.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>write_to_uart</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>transmit/buf_0/valid_write</twComp><twBEL>transmit/buf_0/valid_lut</twBEL></twPathDel><twPathDel><twSite>SLICE.BX</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>transmit/buf_0/valid_write</twComp></twPathDel><twPathDel><twSite>SLICE.COUT</twSite><twDelType>Tbxcy</twDelType><twDelInfo twEdge="twRising">0.656</twDelInfo><twComp>transmit/buf_0/pointer&lt;0&gt;</twComp><twBEL>transmit/buf_0/count_muxcy_0</twBEL><twBEL>transmit/buf_0/count_muxcy_1</twBEL></twPathDel><twPathDel><twSite>SLICE.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>transmit/buf_0/count_carry&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tciny</twDelType><twDelInfo twEdge="twRising">0.728</twDelInfo><twComp>transmit/buf_0/pointer&lt;2&gt;</twComp><twBEL>transmit/buf_0/count_muxcy_2</twBEL><twBEL>transmit/buf_0/count_xor</twBEL></twPathDel><twPathDel><twSite>SLICE.DY</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>transmit/buf_0/next_count&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.CLK</twSite><twDelType>Tdyck</twDelType><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>transmit/buf_0/pointer&lt;2&gt;</twComp><twBEL>transmit/buf_0/register_bit_3</twBEL></twPathDel><twLogDel>4.372</twLogDel><twRouteDel>0.900</twRouteDel><twTotDel>5.272</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">clk50MHz</twDestClk><twPctLog>82.9</twPctLog><twPctRoute>17.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>14.728</twSlack><twSrc BELType="RAM">my_program/ram_1024_x_18.A</twSrc><twDest BELType="FF">transmit/buf_0/register_bit_3</twDest><twTotPathDel>5.272</twTotPathDel><twDelConst>20.000</twDelConst><twClkUncert>0.000</twClkUncert><twDetPath maxSiteLen="11"><twSrc BELType='RAM'>my_program/ram_1024_x_18.A</twSrc><twDest BELType='FF'>transmit/buf_0/register_bit_3</twDest><twLogLvls>8</twLogLvls><twSrcSite>RAMB16.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk50MHz</twSrcClk><twPathDel><twSite>RAMB16.DOA5</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">1.401</twDelInfo><twComp>my_program/ram_1024_x_18</twComp><twBEL>my_program/ram_1024_x_18.A</twBEL></twPathDel><twPathDel><twSite>SLICE.G2</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instruction&lt;5&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.275</twDelInfo><twComp>my_kcpsm3/sy&lt;3&gt;</twComp><twBEL>my_kcpsm3/reg_loop_register_bit_4/DP</twBEL></twPathDel><twPathDel><twSite>SLICE.G3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>my_kcpsm3/sy&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.275</twDelInfo><twComp>N91</twComp><twBEL>my_kcpsm3/operand_select_mux_4</twBEL></twPathDel><twPathDel><twSite>SLICE.F1</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>port_id&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>N91</twComp><twBEL>Ker0_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE.G4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>N91</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.275</twDelInfo><twComp>write_to_uart</twComp><twBEL>Ker0</twBEL></twPathDel><twPathDel><twSite>SLICE.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>N01</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>write_to_uart</twComp><twBEL>write_to_uart1</twBEL></twPathDel><twPathDel><twSite>SLICE.F2</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>write_to_uart</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>transmit/buf_0/valid_write</twComp><twBEL>transmit/buf_0/valid_lut</twBEL></twPathDel><twPathDel><twSite>SLICE.BX</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>transmit/buf_0/valid_write</twComp></twPathDel><twPathDel><twSite>SLICE.COUT</twSite><twDelType>Tbxcy</twDelType><twDelInfo twEdge="twRising">0.656</twDelInfo><twComp>transmit/buf_0/pointer&lt;0&gt;</twComp><twBEL>transmit/buf_0/count_muxcy_0</twBEL><twBEL>transmit/buf_0/count_muxcy_1</twBEL></twPathDel><twPathDel><twSite>SLICE.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>transmit/buf_0/count_carry&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.Y</twSite><twDelType>Tciny</twDelType><twDelInfo twEdge="twRising">0.728</twDelInfo><twComp>transmit/buf_0/pointer&lt;2&gt;</twComp><twBEL>transmit/buf_0/count_muxcy_2</twBEL><twBEL>transmit/buf_0/count_xor</twBEL></twPathDel><twPathDel><twSite>SLICE.DY</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>transmit/buf_0/next_count&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE.CLK</twSite><twDelType>Tdyck</twDelType><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>transmit/buf_0/pointer&lt;2&gt;</twComp><twBEL>transmit/buf_0/register_bit_3</twBEL></twPathDel><twLogDel>4.372</twLogDel><twRouteDel>0.900</twRouteDel><twTotDel>5.272</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">clk50MHz</twDestClk><twPctLog>82.9</twPctLog><twPctRoute>17.1</twPctRoute></twDetPath></twConstPath></twPathRpt></twConst><twConst twConstType="twPathConst"><twConstHead><twConstName>OFFSET = IN 6 ns BEFORE COMP &quot;clk&quot;;</twConstName><twItemCnt>21</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twMinOff>2.741</twMinOff></twConstHead><twPathRpt><twConstOffIn  twDurationNotSpecified = "true"><twSlack>3.259</twSlack><twSrc BELType="PAD">switches&lt;0&gt;</twSrc><twDest BELType="FF">in_port_0</twDest><twClkDel>-0.747</twClkDel><twClkSrc>clk</twClkSrc><twClkDest>in_port&lt;0&gt;</twClkDest><twOff>6.000</twOff><twOffSrc>switches&lt;0&gt;</twOffSrc><twOffDest>clk</twOffDest><twClkUncert>0.000</twClkUncert><twDataPath maxSiteLen="9"><twSrc BELType='PAD'>switches&lt;0&gt;</twSrc><twDest BELType='FF'>in_port_0</twDest><twLogLvls>4</twLogLvls><twSrcSite>IOB.PAD</twSrcSite><twPathDel><twSite>IOB.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.832</twDelInfo><twComp>switches&lt;0&gt;</twComp><twBEL>switches&lt;0&gt;</twBEL><twBEL>switches_0_IBUF</twBEL></twPathDel><twPathDel><twSite>SLICE.F2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>switches_0_IBUF</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>N73</twComp><twBEL>_n0002&lt;0&gt;18</twBEL></twPathDel><twPathDel><twSite>SLICE.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>N73</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>N84</twComp><twBEL>_n0002&lt;0&gt;33</twBEL></twPathDel><twPathDel><twSite>SLICE.F1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>N84</twComp></twPathDel><twPathDel><twSite>SLICE.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.254</twDelInfo><twComp>in_port&lt;0&gt;</twComp><twBEL>_n0002&lt;0&gt;44</twBEL></twPathDel><twPathDel><twSite>SLICE.DX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">0.100</twDelInfo><twComp>_n0002&lt;0&gt;44/O</twComp></twPathDel><twPathDel><twSite>SLICE.CLK</twSite><twDelType>Tdxck</twDelType><twDelInfo twEdge="twFalling">0.000</twDelInfo><twComp>in_port&lt;0&gt;</twComp><twBEL>in_port_0</twBEL></twPathDel><twLogDel>1.594</twLogDel><twRouteDel>0.400</twRouteDel><twTotDel>1.994</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">clk50MHz</twDestClk><twPctLog>79.9</twPctLog><twPctRoute>20.1</twPctRoute></twDataPath><twClkPath maxSiteLen="10"><twSrc BELType='PAD'>clk</twSrc><twDest BELType='FF'>in_port_0</twDest><twLogLvls>3</twLogLvls><twSrcSite>IOB.PAD</twSrcSite><twPathDel><twSite>IOB.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.666</twDelInfo><twComp>clk</twComp><twBEL>clk</twBEL><twBEL>instance_name/CLKIN_IBUFG_INST</twBEL></twPathDel><twPathDel><twSite>DCM.CLKIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKIN_IBUFG_OUT</twComp></twPathDel><twPathDel><twSite>DCM.CLKFX</twSite><twDelType>Tdcmino</twDelType><twDelInfo twEdge="twRising">-1.756</twDelInfo><twComp>instance_name/DCM_INST</twComp><twBEL>instance_name/DCM_INST</twBEL></twPathDel><twPathDel><twSite>BUFGMUX.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKFX_BUF</twComp></twPathDel><twPathDel><twSite>BUFGMUX.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>instance_name/CLKFX_BUFG_INST</twComp><twBEL>instance_name/CLKFX_BUFG_INST</twBEL></twPathDel><twPathDel><twSite>SLICE.CLK</twSite><twDelType>net</twDelType><twFanCnt>127</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>clk50MHz</twComp></twPathDel><twLogDel>-1.047</twLogDel><twRouteDel>0.300</twRouteDel><twTotDel>-0.747</twTotDel></twClkPath></twConstOffIn></twPathRpt><twPathRpt><twConstOffIn  twDurationNotSpecified = "true"><twSlack>3.785</twSlack><twSrc BELType="PAD">rst</twSrc><twDest BELType="FF">transmit/buf_0/register_bit_2</twDest><twClkDel>-0.747</twClkDel><twClkSrc>clk</twClkSrc><twClkDest>transmit/buf_0/pointer&lt;2&gt;</twClkDest><twOff>6.000</twOff><twOffSrc>rst</twOffSrc><twOffDest>clk</twOffDest><twClkUncert>0.000</twClkUncert><twDataPath maxSiteLen="9"><twSrc BELType='PAD'>rst</twSrc><twDest BELType='FF'>transmit/buf_0/register_bit_2</twDest><twLogLvls>1</twLogLvls><twSrcSite>IOB.PAD</twSrcSite><twPathDel><twSite>IOB.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twFalling">0.832</twDelInfo><twComp>rst</twComp><twBEL>rst</twBEL><twBEL>rst_IBUF</twBEL></twPathDel><twPathDel><twSite>SLICE.SR</twSite><twDelType>net</twDelType><twFanCnt>29</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">0.100</twDelInfo><twComp>rst_IBUF</twComp></twPathDel><twPathDel><twSite>SLICE.CLK</twSite><twDelType>Tsrck</twDelType><twDelInfo twEdge="twFalling">0.536</twDelInfo><twComp>transmit/buf_0/pointer&lt;2&gt;</twComp><twBEL>transmit/buf_0/register_bit_2</twBEL></twPathDel><twLogDel>1.368</twLogDel><twRouteDel>0.100</twRouteDel><twTotDel>1.468</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">clk50MHz</twDestClk><twPctLog>93.2</twPctLog><twPctRoute>6.8</twPctRoute></twDataPath><twClkPath maxSiteLen="10"><twSrc BELType='PAD'>clk</twSrc><twDest BELType='FF'>transmit/buf_0/register_bit_2</twDest><twLogLvls>3</twLogLvls><twSrcSite>IOB.PAD</twSrcSite><twPathDel><twSite>IOB.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.666</twDelInfo><twComp>clk</twComp><twBEL>clk</twBEL><twBEL>instance_name/CLKIN_IBUFG_INST</twBEL></twPathDel><twPathDel><twSite>DCM.CLKIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKIN_IBUFG_OUT</twComp></twPathDel><twPathDel><twSite>DCM.CLKFX</twSite><twDelType>Tdcmino</twDelType><twDelInfo twEdge="twRising">-1.756</twDelInfo><twComp>instance_name/DCM_INST</twComp><twBEL>instance_name/DCM_INST</twBEL></twPathDel><twPathDel><twSite>BUFGMUX.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKFX_BUF</twComp></twPathDel><twPathDel><twSite>BUFGMUX.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>instance_name/CLKFX_BUFG_INST</twComp><twBEL>instance_name/CLKFX_BUFG_INST</twBEL></twPathDel><twPathDel><twSite>SLICE.CLK</twSite><twDelType>net</twDelType><twFanCnt>127</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>clk50MHz</twComp></twPathDel><twLogDel>-1.047</twLogDel><twRouteDel>0.300</twRouteDel><twTotDel>-0.747</twTotDel></twClkPath></twConstOffIn></twPathRpt><twPathRpt><twConstOffIn  twDurationNotSpecified = "true"><twSlack>3.785</twSlack><twSrc BELType="PAD">rst</twSrc><twDest BELType="FF">transmit/buf_0/register_bit_3</twDest><twClkDel>-0.747</twClkDel><twClkSrc>clk</twClkSrc><twClkDest>transmit/buf_0/pointer&lt;2&gt;</twClkDest><twOff>6.000</twOff><twOffSrc>rst</twOffSrc><twOffDest>clk</twOffDest><twClkUncert>0.000</twClkUncert><twDataPath maxSiteLen="9"><twSrc BELType='PAD'>rst</twSrc><twDest BELType='FF'>transmit/buf_0/register_bit_3</twDest><twLogLvls>1</twLogLvls><twSrcSite>IOB.PAD</twSrcSite><twPathDel><twSite>IOB.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twFalling">0.832</twDelInfo><twComp>rst</twComp><twBEL>rst</twBEL><twBEL>rst_IBUF</twBEL></twPathDel><twPathDel><twSite>SLICE.SR</twSite><twDelType>net</twDelType><twFanCnt>29</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">0.100</twDelInfo><twComp>rst_IBUF</twComp></twPathDel><twPathDel><twSite>SLICE.CLK</twSite><twDelType>Tsrck</twDelType><twDelInfo twEdge="twFalling">0.536</twDelInfo><twComp>transmit/buf_0/pointer&lt;2&gt;</twComp><twBEL>transmit/buf_0/register_bit_3</twBEL></twPathDel><twLogDel>1.368</twLogDel><twRouteDel>0.100</twRouteDel><twTotDel>1.468</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="0.000">clk50MHz</twDestClk><twPctLog>93.2</twPctLog><twPctRoute>6.8</twPctRoute></twDataPath><twClkPath maxSiteLen="10"><twSrc BELType='PAD'>clk</twSrc><twDest BELType='FF'>transmit/buf_0/register_bit_3</twDest><twLogLvls>3</twLogLvls><twSrcSite>IOB.PAD</twSrcSite><twPathDel><twSite>IOB.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.666</twDelInfo><twComp>clk</twComp><twBEL>clk</twBEL><twBEL>instance_name/CLKIN_IBUFG_INST</twBEL></twPathDel><twPathDel><twSite>DCM.CLKIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKIN_IBUFG_OUT</twComp></twPathDel><twPathDel><twSite>DCM.CLKFX</twSite><twDelType>Tdcmino</twDelType><twDelInfo twEdge="twRising">-1.756</twDelInfo><twComp>instance_name/DCM_INST</twComp><twBEL>instance_name/DCM_INST</twBEL></twPathDel><twPathDel><twSite>BUFGMUX.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKFX_BUF</twComp></twPathDel><twPathDel><twSite>BUFGMUX.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.043</twDelInfo><twComp>instance_name/CLKFX_BUFG_INST</twComp><twBEL>instance_name/CLKFX_BUFG_INST</twBEL></twPathDel><twPathDel><twSite>SLICE.CLK</twSite><twDelType>net</twDelType><twFanCnt>127</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>clk50MHz</twComp></twPathDel><twLogDel>-1.047</twLogDel><twRouteDel>0.300</twRouteDel><twTotDel>-0.747</twTotDel></twClkPath></twConstOffIn></twPathRpt></twConst><twConst twConstType="twPathConst"><twConstHead><twConstName>OFFSET = OUT 7.5 ns AFTER COMP &quot;clk&quot;;</twConstName><twItemCnt>9</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twMinOff>2.197</twMinOff></twConstHead><twPathRpt><twConstOffOut twDataPathType = "twDataPathMaxDelay"><twSlack>5.303</twSlack><twSrc BELType="FF">leds_2</twSrc><twDest BELType="PAD">leds&lt;2&gt;</twDest><twClkDel>-0.140</twClkDel><twClkSrc>clk</twClkSrc><twClkDest>leds&lt;2&gt;</twClkDest><twDataDel>2.337</twDataDel><twDataSrc>leds&lt;2&gt;</twDataSrc><twDataDest>leds&lt;2&gt;</twDataDest><twOff>7.500</twOff><twOffSrc>clk</twOffSrc><twOffDest>leds&lt;2&gt;</twOffDest><twClkUncert>0.000</twClkUncert><twClkPath maxSiteLen="10"><twSrc BELType='PAD'>clk</twSrc><twDest BELType='FF'>leds_2</twDest><twLogLvls>3</twLogLvls><twSrcSite>IOB.PAD</twSrcSite><twPathDel><twSite>IOB.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.832</twDelInfo><twComp>clk</twComp><twBEL>clk</twBEL><twBEL>instance_name/CLKIN_IBUFG_INST</twBEL></twPathDel><twPathDel><twSite>DCM.CLKIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKIN_IBUFG_OUT</twComp></twPathDel><twPathDel><twSite>DCM.CLKFX</twSite><twDelType>Tdcmino</twDelType><twDelInfo twEdge="twRising">-1.322</twDelInfo><twComp>instance_name/DCM_INST</twComp><twBEL>instance_name/DCM_INST</twBEL></twPathDel><twPathDel><twSite>BUFGMUX.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKFX_BUF</twComp></twPathDel><twPathDel><twSite>BUFGMUX.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.050</twDelInfo><twComp>instance_name/CLKFX_BUFG_INST</twComp><twBEL>instance_name/CLKFX_BUFG_INST</twBEL></twPathDel><twPathDel><twSite>IOB.OTCLK1</twSite><twDelType>net</twDelType><twFanCnt>127</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>clk50MHz</twComp></twPathDel><twLogDel>-0.440</twLogDel><twRouteDel>0.300</twRouteDel><twTotDel>-0.140</twTotDel></twClkPath><twDataPath maxSiteLen="7"><twSrc BELType='FF'>leds_2</twSrc><twDest BELType='PAD'>leds&lt;2&gt;</twDest><twLogLvls>0</twLogLvls><twSrcSite>IOB.OTCLK1</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk50MHz</twSrcClk><twPathDel><twSite>IOB.PAD</twSite><twDelType>Tiockp</twDelType><twDelInfo twEdge="twRising">2.337</twDelInfo><twComp>leds&lt;2&gt;</twComp><twBEL>leds_2</twBEL><twBEL>leds_2_OBUF</twBEL><twBEL>leds&lt;2&gt;</twBEL></twPathDel><twLogDel>2.337</twLogDel><twRouteDel>0.000</twRouteDel><twTotDel>2.337</twTotDel><twPctLog>100.0</twPctLog><twPctRoute>0.0</twPctRoute></twDataPath></twConstOffOut></twPathRpt><twPathRpt><twConstOffOut twDataPathType = "twDataPathMaxDelay"><twSlack>5.303</twSlack><twSrc BELType="FF">leds_0</twSrc><twDest BELType="PAD">leds&lt;0&gt;</twDest><twClkDel>-0.140</twClkDel><twClkSrc>clk</twClkSrc><twClkDest>leds&lt;0&gt;</twClkDest><twDataDel>2.337</twDataDel><twDataSrc>leds&lt;0&gt;</twDataSrc><twDataDest>leds&lt;0&gt;</twDataDest><twOff>7.500</twOff><twOffSrc>clk</twOffSrc><twOffDest>leds&lt;0&gt;</twOffDest><twClkUncert>0.000</twClkUncert><twClkPath maxSiteLen="10"><twSrc BELType='PAD'>clk</twSrc><twDest BELType='FF'>leds_0</twDest><twLogLvls>3</twLogLvls><twSrcSite>IOB.PAD</twSrcSite><twPathDel><twSite>IOB.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.832</twDelInfo><twComp>clk</twComp><twBEL>clk</twBEL><twBEL>instance_name/CLKIN_IBUFG_INST</twBEL></twPathDel><twPathDel><twSite>DCM.CLKIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKIN_IBUFG_OUT</twComp></twPathDel><twPathDel><twSite>DCM.CLKFX</twSite><twDelType>Tdcmino</twDelType><twDelInfo twEdge="twRising">-1.322</twDelInfo><twComp>instance_name/DCM_INST</twComp><twBEL>instance_name/DCM_INST</twBEL></twPathDel><twPathDel><twSite>BUFGMUX.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKFX_BUF</twComp></twPathDel><twPathDel><twSite>BUFGMUX.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.050</twDelInfo><twComp>instance_name/CLKFX_BUFG_INST</twComp><twBEL>instance_name/CLKFX_BUFG_INST</twBEL></twPathDel><twPathDel><twSite>IOB.OTCLK1</twSite><twDelType>net</twDelType><twFanCnt>127</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>clk50MHz</twComp></twPathDel><twLogDel>-0.440</twLogDel><twRouteDel>0.300</twRouteDel><twTotDel>-0.140</twTotDel></twClkPath><twDataPath maxSiteLen="7"><twSrc BELType='FF'>leds_0</twSrc><twDest BELType='PAD'>leds&lt;0&gt;</twDest><twLogLvls>0</twLogLvls><twSrcSite>IOB.OTCLK1</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk50MHz</twSrcClk><twPathDel><twSite>IOB.PAD</twSite><twDelType>Tiockp</twDelType><twDelInfo twEdge="twRising">2.337</twDelInfo><twComp>leds&lt;0&gt;</twComp><twBEL>leds_0</twBEL><twBEL>leds_0_OBUF</twBEL><twBEL>leds&lt;0&gt;</twBEL></twPathDel><twLogDel>2.337</twLogDel><twRouteDel>0.000</twRouteDel><twTotDel>2.337</twTotDel><twPctLog>100.0</twPctLog><twPctRoute>0.0</twPctRoute></twDataPath></twConstOffOut></twPathRpt><twPathRpt><twConstOffOut twDataPathType = "twDataPathMaxDelay"><twSlack>5.303</twSlack><twSrc BELType="FF">leds_1</twSrc><twDest BELType="PAD">leds&lt;1&gt;</twDest><twClkDel>-0.140</twClkDel><twClkSrc>clk</twClkSrc><twClkDest>leds&lt;1&gt;</twClkDest><twDataDel>2.337</twDataDel><twDataSrc>leds&lt;1&gt;</twDataSrc><twDataDest>leds&lt;1&gt;</twDataDest><twOff>7.500</twOff><twOffSrc>clk</twOffSrc><twOffDest>leds&lt;1&gt;</twOffDest><twClkUncert>0.000</twClkUncert><twClkPath maxSiteLen="10"><twSrc BELType='PAD'>clk</twSrc><twDest BELType='FF'>leds_1</twDest><twLogLvls>3</twLogLvls><twSrcSite>IOB.PAD</twSrcSite><twPathDel><twSite>IOB.I</twSite><twDelType>Tiopi</twDelType><twDelInfo twEdge="twRising">0.832</twDelInfo><twComp>clk</twComp><twBEL>clk</twBEL><twBEL>instance_name/CLKIN_IBUFG_INST</twBEL></twPathDel><twPathDel><twSite>DCM.CLKIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKIN_IBUFG_OUT</twComp></twPathDel><twPathDel><twSite>DCM.CLKFX</twSite><twDelType>Tdcmino</twDelType><twDelInfo twEdge="twRising">-1.322</twDelInfo><twComp>instance_name/DCM_INST</twComp><twBEL>instance_name/DCM_INST</twBEL></twPathDel><twPathDel><twSite>BUFGMUX.I0</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>instance_name/CLKFX_BUF</twComp></twPathDel><twPathDel><twSite>BUFGMUX.O</twSite><twDelType>Tgi0o</twDelType><twDelInfo twEdge="twRising">0.050</twDelInfo><twComp>instance_name/CLKFX_BUFG_INST</twComp><twBEL>instance_name/CLKFX_BUFG_INST</twBEL></twPathDel><twPathDel><twSite>IOB.OTCLK1</twSite><twDelType>net</twDelType><twFanCnt>127</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.100</twDelInfo><twComp>clk50MHz</twComp></twPathDel><twLogDel>-0.440</twLogDel><twRouteDel>0.300</twRouteDel><twTotDel>-0.140</twTotDel></twClkPath><twDataPath maxSiteLen="7"><twSrc BELType='FF'>leds_1</twSrc><twDest BELType='PAD'>leds&lt;1&gt;</twDest><twLogLvls>0</twLogLvls><twSrcSite>IOB.OTCLK1</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk50MHz</twSrcClk><twPathDel><twSite>IOB.PAD</twSite><twDelType>Tiockp</twDelType><twDelInfo twEdge="twRising">2.337</twDelInfo><twComp>leds&lt;1&gt;</twComp><twBEL>leds_1</twBEL><twBEL>leds_1_OBUF</twBEL><twBEL>leds&lt;1&gt;</twBEL></twPathDel><twLogDel>2.337</twLogDel><twRouteDel>0.000</twRouteDel><twTotDel>2.337</twTotDel><twPctLog>100.0</twPctLog><twPctRoute>0.0</twPctRoute></twDataPath></twConstOffOut></twPathRpt></twConst><twUnmetConstCnt>0</twUnmetConstCnt><twDataSheet twNameLen="15"><twSUH2ClkList twDestWidth = "11" twPhaseWidth = "8"><twDest>clk</twDest><twSUH2Clk ><twSrc>rs232_rx</twSrc><twSUHTime twInternalClk ="clk50MHz" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">1.689</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.866</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>rst</twSrc><twSUHTime twInternalClk ="clk50MHz" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.215</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.919</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switches&lt;0&gt;</twSrc><twSUHTime twInternalClk ="clk50MHz" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.741</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.697</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switches&lt;1&gt;</twSrc><twSUHTime twInternalClk ="clk50MHz" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.054</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.108</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switches&lt;2&gt;</twSrc><twSUHTime twInternalClk ="clk50MHz" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.054</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.108</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switches&lt;3&gt;</twSrc><twSUHTime twInternalClk ="clk50MHz" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.033</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.091</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switches&lt;4&gt;</twSrc><twSUHTime twInternalClk ="clk50MHz" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.054</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.108</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switches&lt;5&gt;</twSrc><twSUHTime twInternalClk ="clk50MHz" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.033</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.091</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switches&lt;6&gt;</twSrc><twSUHTime twInternalClk ="clk50MHz" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.033</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.091</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switches&lt;7&gt;</twSrc><twSUHTime twInternalClk ="clk50MHz" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.033</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.091</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2OutList twDestWidth = "8" twPhaseWidth = "8"><twSrc>clk</twSrc><twClk2Out  twOutPad = "leds&lt;0&gt;" twMinTime = "1.274" twMinEdge ="twRising" twMaxTime = "2.197" twMaxEdge ="twRising" twInternalClk="clk50MHz" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "leds&lt;1&gt;" twMinTime = "1.274" twMinEdge ="twRising" twMaxTime = "2.197" twMaxEdge ="twRising" twInternalClk="clk50MHz" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "leds&lt;2&gt;" twMinTime = "1.274" twMinEdge ="twRising" twMaxTime = "2.197" twMaxEdge ="twRising" twInternalClk="clk50MHz" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "leds&lt;3&gt;" twMinTime = "1.274" twMinEdge ="twRising" twMaxTime = "2.197" twMaxEdge ="twRising" twInternalClk="clk50MHz" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "leds&lt;4&gt;" twMinTime = "1.274" twMinEdge ="twRising" twMaxTime = "2.197" twMaxEdge ="twRising" twInternalClk="clk50MHz" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "leds&lt;5&gt;" twMinTime = "1.274" twMinEdge ="twRising" twMaxTime = "2.197" twMaxEdge ="twRising" twInternalClk="clk50MHz" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "leds&lt;6&gt;" twMinTime = "1.274" twMinEdge ="twRising" twMaxTime = "2.197" twMaxEdge ="twRising" twInternalClk="clk50MHz" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "leds&lt;7&gt;" twMinTime = "1.274" twMinEdge ="twRising" twMaxTime = "2.197" twMaxEdge ="twRising" twInternalClk="clk50MHz" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "rs232_tx" twMinTime = "1.274" twMinEdge ="twRising" twMaxTime = "2.197" twMaxEdge ="twRising" twInternalClk="clk50MHz" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList twDestWidth = "3"><twDest>clk</twDest><twClk2SU><twSrc>clk</twSrc><twRiseRise>5.272</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables><twOffsetOutTable twDestWidth = "8" twMinSlack = "5.303" twMaxSlack = "5.303" twRelSkew = "0.000" ><twConstName>OFFSET = OUT 7.5 ns AFTER COMP &quot;clk&quot;;</twConstName><twOffOutTblRow  twOutPad = "leds&lt;0&gt;" twSlack = "5.303" twRelSkew = "0.000" ></twOffOutTblRow><twOffOutTblRow  twOutPad = "leds&lt;1&gt;" twSlack = "5.303" twRelSkew = "0.000" ></twOffOutTblRow><twOffOutTblRow  twOutPad = "leds&lt;2&gt;" twSlack = "5.303" twRelSkew = "0.000" ></twOffOutTblRow><twOffOutTblRow  twOutPad = "leds&lt;3&gt;" twSlack = "5.303" twRelSkew = "0.000" ></twOffOutTblRow><twOffOutTblRow  twOutPad = "leds&lt;4&gt;" twSlack = "5.303" twRelSkew = "0.000" ></twOffOutTblRow><twOffOutTblRow  twOutPad = "leds&lt;5&gt;" twSlack = "5.303" twRelSkew = "0.000" ></twOffOutTblRow><twOffOutTblRow  twOutPad = "leds&lt;6&gt;" twSlack = "5.303" twRelSkew = "0.000" ></twOffOutTblRow><twOffOutTblRow  twOutPad = "leds&lt;7&gt;" twSlack = "5.303" twRelSkew = "0.000" ></twOffOutTblRow><twOffOutTblRow  twOutPad = "rs232_tx" twSlack = "5.303" twRelSkew = "0.000" ></twOffOutTblRow></twOffsetOutTable></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum><twErrCnt>0</twErrCnt><twScore>0</twScore><twConstCov><twPathCnt>8869</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>1805</twConnCnt></twConstCov><twStats><twMinPer>5.272</twMinPer><twFootnote number="1" /><twMaxFreq>189.681</twMaxFreq><twMinInBeforeClk>2.741</twMinInBeforeClk><twMinOutAfterClk>2.197</twMinOutAfterClk></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Wed May 24 09:46:32 2006</twTimestamp></twFoot><twClientInfo><twClientName>Timing Analyzer</twClientName><twAttrList><twAttrListItem><twName>Timing Analyzer Settings</twName><twValue>OpenPCF C:\XUP\Markets\PLDs\Workshops\courses\v81_fpga_flow\xupv2pro\labsolutions\verilog\lab3\time_const\loopback.pcf
Speed -7
IncludeNets
ExcludeNets
SelectFailingTimingConstraint False
IncludeNoTimingConstraint False
Report normal
MaxPathsPerTimingConstraint 3
ReportFastestPaths False
GenerateDataSheet True
GenerateTimeGroup False
DefineEndpoints ToAll
DefineEndpoints FromAll
OmitUserConstraints False
DropTimingConstraint
SetForce Off
ProratingOptions  

Peak Memory Usage: 183 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>