loopback.mrp

Xilinx的培训教程的源码 virtex

Release 8.2.01i Map I.32
Xilinx Mapping Report File for Design 'loopback'

Design Information
------------------
Command Line   : map loopback.ngd loopback.pcf 
Target Device  : xc2vp30
Target Package : ff896
Target Speed   : -7
Mapper Version : virtex2p -- $Revision: 1.34.32.1 $
Mapped Date    : Wed Aug 16 11:32:44 2006

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         141 out of  27,392    1%
  Number of 4 input LUTs:             167 out of  27,392    1%
Logic Distribution:
  Number of occupied Slices:          158 out of  13,696    1%
  Number of Slices containing only related logic:     158 out of     158  100%
  Number of Slices containing unrelated logic:          0 out of     158    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            281 out of  27,392    1%
  Number used as logic:               167
  Number used as a route-thru:         10
  Number used for Dual Port RAMs:      16
    (Two LUTs used per Dual Port RAM)
  Number used for 32x1 RAMs:           52
    (Two LUTs used per 32x1 RAM)
  Number used as Shift registers:      36

  Number of bonded IOBs:               21 out of     556    3%
  Number of PPC405s:                   0 out of       2    0%
  Number of Block RAMs:                 1 out of     136    1%
  Number of GCLKs:                      2 out of      16   12%
  Number of DCMs:                       1 out of       8   12%
  Number of GTs:                        0 out of       8    0%
  Number of GT10s:                      0 out of       0    0%

Total equivalent gate count for design:  86,163
Additional JTAG gate count for IOBs:  1,008
Peak Memory Usage:  205 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFG symbol "instance_name/CLK0_BUFG_INST" (output
   signal=instance_name/CLK0_OUT),
   BUFG symbol "instance_name/CLKFX_BUFG_INST" (output signal=clk50MHz)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   instance_name/DCM_INST/instance_name/DCM_INST, consult the device Interactive
   Data Sheet.

Section 4 - Removed Logic Summary
---------------------------------
   5 block(s) removed
   9 block(s) optimized away
   7 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic

The signal "my_kcpsm3/interrupt_ack" is unused and has been removed.
 Unused block "my_kcpsm3/ack_flop" (FF) removed.
The signal "my_kcpsm3/sel_shadow_carry" is unused and has been removed.
 Unused block "my_kcpsm3/sel_shadow_carry_lut" (ROM) removed.
The signal "my_kcpsm3/int_pulse" is unused and has been removed.
The signal "my_kcpsm3/int_enable_value" is unused and has been removed.
 Unused block "my_kcpsm3/int_value_lut" (ROM) removed.
The signal "my_kcpsm3/int_enable" is unused and has been removed.
 Unused block "my_kcpsm3/int_enable_flop" (SFF) removed.
  The signal "my_kcpsm3/int_update_enable" is unused and has been removed.
   Unused block "my_kcpsm3/int_update_lut" (ROM) removed.
The signal "my_kcpsm3/not_active_interrupt" is unused and has been removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC
FDR 		my_kcpsm3/int_capture_flop
   optimized to 0
FDR 		my_kcpsm3/int_flop
   optimized to 0
LUT4 		my_kcpsm3/int_pulse_lut
FDE 		my_kcpsm3/shadow_carry_flop
   optimized to 0
FDE 		my_kcpsm3/shadow_zero_flop
   optimized to 0
INV 		my_kcpsm3/stack_count_inv
MUXCY 		my_kcpsm3/sel_shadow_muxcy

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| leds<0>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| leds<1>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| leds<2>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| leds<3>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| leds<4>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| leds<5>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| leds<6>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| leds<7>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| lock                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| rs232_rx                           | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| rs232_tx                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| rst                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| switches<0>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| switches<1>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| switches<2>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| switches<3>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| switches<4>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| switches<5>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| switches<6>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| switches<7>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings