map.xmsgs
来自「Xilinx的培训教程的源码 virtex」· XMSGS 代码 · 共 23 行
XMSGS
23 行
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>
<msg type="info" file="MapLib" num="535" delta="unknown" >The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFG symbol "instance_name/CLK0_BUFG_INST" (output signal=instance_name/CLK0_OUT),
BUFG symbol "instance_name/CLKFX_BUFG_INST" (output signal=clk50MHz)</arg>
</msg>
<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>
<msg type="info" file="PhysDesignRules" num="772">To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp instance_name/DCM_INST/instance_name/DCM_INST, consult the device Interactive Data Sheet.
</msg>
</messages>
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