blk_mem_gen_release_notes.txt

Xilinx的培训教程的源码 virtex

COPYRIGHT (c) 2006 XILINX, INC.
ALL RIGHTS RESERVED

Core name            : Block Memory Generator 
Version              : v2.1
Release Date         : July 13, 2006
File                 : blk_mem_gen_release_notes.txt

Revision History
Date     By            Version   Change Description
========================================================================
01/2006  Xilinx, Inc.  1.1       Initial creation.
06/2006  Xilinx, Inc.  2.1       Version 2.1
========================================================================

INTRODUCTION
RELEASE NOTES
  1. General Core Design
    1.1 Enhancements
    1.2 Resolved Issues
    1.3 Outstanding Issues
  2. General Simulation
    2.1 Enhancements
    2.2 Resolved Issues
    2.3 Outstanding Issues
  3. Documentation
    3.1 Enhancements
    3.2 Resolved Issues
    3.3 Outstanding Issues
OTHER GENERAL INFORMATION
TECHNICAL SUPPORT

========================================================================

INTRODUCTION
============
Thank you using the Block Memory Generator core from
Xilinx!  In order to obtain the latest core updates and documentation, 
please visit the Intellectual Property page located at:
http://www.xilinx.com/ipcenter/index.htm
This document contains the release notes for Block Memory Generator v2.1
which includes enhancements, resolved issues and outstanding known
issues.
For the most up-to-date release note information, please refer to Xilinx
Answer Record 23489 at
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=23489

RELEASE NOTES
=============
This section lists any enhancements, resolved issues and outstanding
known issues.


1. General Core Design
  1.1 Enhancements
    1.1.1 Added Support for Virtex-5, including both RAMB18 and RAMB36
          primitives

    1.1.2 8-bit byte-write enable is now supported for Virtex-4 and
          Virtex-5 architectures

  1.2 Resolved Issues
    1.2.1 Timing Performance severly impacted by XST synthesis bug in
          mux structure.
          Change Request: 229624

    1.2.2 GUI doesn't restrict data width ratios when byte-write
          feature is used.
          Change Request: 223314
          When using the byte-writes, no two data widths can have a
	  ratio greater than 4:1.  If the ratio is greater than 4:1, a
	  netlist will not be generated.

    1.2.3 XCO file loading error due to byte write enable
          Change Request: 223255

    1.2.4 The Block RAM resource count is not a true indication of the
          block RAM usage.
          Change Request: 229746

    1.2.5 Loading a COE causes Coregen to crash
          Change requests: 225263, 223374, 224234, 223255

  1.3 Outstanding Issues

    1.3.1 Core does not generate for large memories.  Depending on the
          machine Coregen runs on, the maximum size of the memory that
          can be generated will vary.  For example, a Dual Pentium-4
          server running at 3.6GHz with 2 Gig RAM can generate a memory 
          core of size 1.8 MBits or 230 K Bytes.
          Change request: 225405

    1.3.2 Out-of-range address input can cause the core to generate X's
          on the DOUT bus.

    1.3.3 Errors in SDF file during timing simulation
          Change request: 232997, 233001, 233006, 233008

    1.3.4 Verilog Structural Simulation Fails
          Change request: 232994


2. General Simulation
  2.1 Enhancements
      None at this time.

  2.2 Resolved Issues
    2.2.1 Incorrect output when reset and write operation occur in the
          same clock cycle
          Change Request: 223313
          When a port is configured with "NO_CHANGE" operating mode
          and has a set/reset pin (SSR), the output changes instead of
          adhering to the "NO_CHANGE" operating mode when a set/reset
          and write operation occur in the same clock cycle.
    
    2.2.2 Core output initializes to 0 instead of the specified
          Output Reset Value
          Change request: 225906

    2.2.3 SSR input does not reset output registers correctly for
          Virtex-II and Virtex-4. 
          Change request: 227669
          The output register stages of the Block Memory Generator core 
          require REGCE to update, but EN to reset using SSR.

  2.3 Outstanding Issues
    2.3.1 Behavioral models do not flag collision for asymmetric
          read-write ports
          Change request: 223085
          Occurs when the core is configured as a true dual port
          memory, the read data width is much larger than the write
          data width and if any of the operating mode is "NO_CHANGE"
          or "WRITE_FIRST".  When a write operation occurs on both
          ports on the same memory space (no write-write collision)
          that is being read out, the simulation models do not flag a
          write-read collision.  Occurs in both behavioral and 
          structural simulations.

3. Documentation
  3.1 Enhancements
    3.1.1 Modified "Output Register" section to more clearly reflect
          actual design behavior.

  3.2 Resolved Issues
    3.2.1 Corrected documentation on NO_CHANGE mode to indicate that
          the output bus is not valid when either byte-write enable
          or asymmetric ports are used.

    3.2.2 Corrected resource utilization tables to indicate LUT 
          resources without route-thru.

    3.2.3 The explanation of the behavior of the enable pin is incorrect
          Change request: 224420

  3.3 Outstanding Issues
      None at this time.


TECHNICAL SUPPORT
=================
The fastest method for obtaining specific technical support for the 
Block Memory Generator core is through the http://support.xilinx.com/
website. Questions are routed to a team of engineers with specific
expertise in using the Block Memory Generator core.  Xilinx will provide
technical support for use of this product as described in the Block
Memory Generator Datasheet. Xilinx cannot guarantee timing,
functionality, or support of this product for designs that do not
follow these guidelines.