loopback.v

Xilinx的培训教程的源码 virtex

// File:  loopback.v
// Date:  01/01/2005
// Name:  Eric Crabill
// 
// This is the top level design for the
// EE178 Lab #4 assignment.

// The `timescale directive specifies what
// the simulation time units are (1 ns here)
// and what the simulator timestep should be
// (1 ps here).

`timescale 1 ns / 1 ps

module loopback(clk, rst, leds, switches, rs232_tx, rs232_rx, lock);

  input         clk, rst;
  output  [7:0] leds;
  input   [7:0] switches;
  input         rs232_rx;
  output        rs232_tx;
  output        lock;

  // Instantiate PicoBlaze and the instruction
  // ROM.  This is simply cut and paste from the
  // example designs that come with PicoBlaze.
  // Interrupts are not used for this design.

  wire    [9:0] address;
  wire   [17:0] instruction;
  wire    [7:0] port_id;
  wire    [7:0] out_port;
  reg     [7:0] in_port;
  wire          write_strobe;
  wire          read_strobe;
  
  wire rst_in;
  wire clk50MHz;
  
  assign rst_in = ~rst;

  kcpsm3 my_kcpsm3 (
    .address(address),
    .instruction(instruction),
    .port_id(port_id),
    .write_strobe(write_strobe),
    .out_port(out_port),
    .read_strobe(read_strobe),
    .in_port(in_port),
    .interrupt(1'b0),
    .interrupt_ack(),
    .reset(rst_in),
    .clk(clk50MHz)
    );

  program my_program (
    .address(address),
    .instruction(instruction),
    .clk(clk50MHz)
    );
	 
  my_dcm instance_name (
    .CLKIN_IN(clk), 
    .RST_IN(rst_in), 
    .CLKFX_OUT(clk50MHz), 
    .CLKIN_IBUFG_OUT(), 
    .CLK0_OUT(CLK0_OUT), 
    .LOCKED_OUT(lock)
    );

  // Implement the 16x bit rate counter
  // for the uart transmit and receive.
  // The system clock is 50 MHz, and the
  // desired baud rate is 9600.  I used
  // the formula in the documentation to
  // calculate the terminal count value.

  reg     [8:0] baud_count;
  reg           en_16_x_baud;

  always @(posedge clk50MHz or posedge rst_in)
  begin
    if (rst_in)
    begin
      baud_count <= 0;
      en_16_x_baud <= 0;
    end
    else
    begin
      if (baud_count == 325)
      begin
        baud_count <= 0;
        en_16_x_baud <= 1;
      end
      else
      begin
        baud_count <= baud_count + 1;
        en_16_x_baud <= 0;
      end
    end
  end

  // Implement the output port logic:
  // leds_out, port 01
  // uart_data_tx, port 03

  wire          write_to_uart;
  wire          write_to_leds;
  wire          buffer_full;
  reg     [7:0] leds;

  assign write_to_uart = write_strobe & (port_id == 8'h03);
  assign write_to_leds = write_strobe & (port_id == 8'h01);

  always @(posedge clk50MHz or posedge rst_in)
  begin
    if (rst_in) leds <= 0;
    else if (write_to_leds) leds <= out_port;
  end

  uart_tx transmit (
    .data_in(out_port), 
    .write_buffer(write_to_uart),
    .reset_buffer(rst_in),
    .en_16_x_baud(en_16_x_baud),
    .serial_out(rs232_tx),
    .buffer_full(buffer_full),
    .buffer_half_full(),
    .clk(clk50MHz)
    );

  // Implement the input port logic:
  // switch_in, port 00
  // uart_data_rx, port 02
  // data_present, port 04
  // buffer_full, port 05

  reg           read_from_uart;
  wire    [7:0] rx_data;
  wire          data_present;

  always @(posedge clk50MHz or posedge rst_in)
  begin
    if (rst_in)
    begin
      in_port <= 0;
      read_from_uart <= 0;
    end
    else
    begin
      case (port_id)
        8'h00: in_port <= switches;
        8'h02: in_port <= rx_data;
        8'h04: in_port <= {7'b0000000, data_present};
        8'h05: in_port <= {7'b0000000, buffer_full};
        default: in_port <= 8'h00;
      endcase
      read_from_uart <= read_strobe & (port_id == 8'h02);
    end
  end

  uart_rx receive (
    .serial_in(rs232_rx),
    .data_out(rx_data),
    .read_buffer(read_from_uart),
    .reset_buffer(rst_in),
    .en_16_x_baud(en_16_x_baud),
    .buffer_data_present(data_present),
    .buffer_full(),
    .buffer_half_full(),
    .clk(clk50MHz)
    );  

endmodule