📄 sp3e1600e_picoblaze_spi_flash_dte_115200_prog.vhd
字号:
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => kcpsm3_reset,
clk => clk);
program_rom: spi_prog
port map( address => address,
instruction => instruction,
proc_reset => kcpsm3_reset,
clk => clk);
--
----------------------------------------------------------------------------------------------------------------------------------
-- Interrupt
----------------------------------------------------------------------------------------------------------------------------------
--
--
-- Interrupt is used to detect when the UART receiver FIFO reaches half full and this is
-- then used to send XON and XOFF flow control characters back to the PC.
--
-- If 'rx_half_full' goes High, an interrupt is generated and the subsequent ISR will transmit
-- an XOFF character to stop the flow of new characters from the PC and allow the FIFO to start to empty.
--
-- If 'rx_half_full' goes Low, an interrupt is generated and the subsequent ISR will transmit
-- an XON character which will allow the PC to send new characters and allow the FIFO to start to fill.
--
interrupt_control: process(clk)
begin
if clk'event and clk='1' then
-- detect change in state of the 'rx_half_full' flag.
previous_rx_half_full <= rx_half_full;
rx_half_full_event <= previous_rx_half_full xor rx_half_full;
-- processor interrupt waits for an acknowledgement
if interrupt_ack='1' then
interrupt <= '0';
elsif rx_half_full_event='1' then
interrupt <= '1';
else
interrupt <= interrupt;
end if;
end if;
end process interrupt_control;
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 input ports
----------------------------------------------------------------------------------------------------------------------------------
--
--
-- UART FIFO status signals to form a bus
--
status_port <= "00" & rx_full & rx_half_full & rx_data_present & tx_full & tx_half_full & tx_data_present;
--
-- The inputs connect via a pipelined multiplexer
--
input_ports: process(clk)
begin
if clk'event and clk='1' then
case port_id(1 downto 0) is
-- read status signals at address 00 hex
when "00" => in_port <= status_port;
-- read UART receive data at address 01 hex
when "01" => in_port <= rx_data;
-- read SPI data input SDO at address 02 hex
-- called SDO because it connects to the data outputs of all the slave devices
-- Normal SDO data is bit7.
-- SDI data from the amplifier is at bit 6 because it is always driving and needs a separate pin.
when "10" => in_port <= spi_sdo & spi_amp_sdo & "000000";
-- Don't care used for all other addresses to ensure minimum logic implementation
when others => in_port <= "XXXXXXXX";
end case;
-- Form read strobe for UART receiver FIFO buffer at address 01 hex.
-- The fact that the read strobe will occur after the actual data is read by
-- the KCPSM3 is acceptable because it is really means 'I have read you'!
if (read_strobe='1' and port_id(1 downto 0)="01") then
read_from_uart <= '1';
else
read_from_uart <= '0';
end if;
end if;
end process input_ports;
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 output ports
----------------------------------------------------------------------------------------------------------------------------------
--
-- adding the output registers to the processor
output_ports: process(clk)
begin
if clk'event and clk='1' then
if write_strobe='1' then
-- Write to SPI data output at address 04 hex.
-- called SDI because it connects to the data inputs of all the slave devices
if port_id(2)='1' then
spi_sdi <= out_port(7);
end if;
-- Write to SPI control at address 08 hex.
if port_id(3)='1' then
spi_sck <= out_port(0);
spi_rom_cs <= out_port(1);
--spare control <= out_port(2);
spi_amp_cs <= out_port(3);
spi_adc_conv <= out_port(4);
spi_dac_cs <= out_port(5);
spi_amp_shdn <= out_port(6);
spi_dac_clr <= out_port(7);
end if;
end if;
end if;
end process output_ports;
--
-- write to UART transmitter FIFO buffer at address 10 hex.
-- This is a combinatorial decode because the FIFO is the 'port register'.
--
write_to_uart <= '1' when (write_strobe='1' and port_id(4)='1') else '0';
--
----------------------------------------------------------------------------------------------------------------------------------
-- UART
----------------------------------------------------------------------------------------------------------------------------------
--
-- Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
-- Each contains an embedded 16-byte FIFO buffer.
--
-- Loop-back on the male connector
transmit: uart_tx_plus
port map ( data_in => out_port,
write_buffer => write_to_uart,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
serial_out => RS232_TXD,
buffer_data_present => tx_data_present,
buffer_full => tx_full,
buffer_half_full => tx_half_full,
clk => clk );
receive: uart_rx
port map ( data_out => rx_data,
read_buffer => read_from_uart,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
serial_in => RS232_RXD,
buffer_data_present => rx_data_present,
buffer_full => rx_full,
buffer_half_full => rx_half_full,
clk => clk );
--
-- Set baud rate to 115200 for the UART communications
-- Requires en_16_x_baud to be 1843200Hz which is a single cycle pulse every 27 cycles at 50MHz
--
baud_timer: process(clk)
begin
if clk'event and clk='1' then
if baud_count=26 then
baud_count <= 0;
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_timer;
--
----------------------------------------------------------------------------------------------------------------------------------
end Behavioral;
------------------------------------------------------------------------------------------------------------------------------------
--
-- END OF FILE spi_flash_memory_uart_programmer.vhd
--
------------------------------------------------------------------------------------------------------------------------------------
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