📄 sp3e1600e_picoblaze_spi_flash_dte_115200_prog.vhd
字号:
--
-- KCPSM3 reference design - PicoBlaze performing programming of SPI Flash Memory
-- type M25P16 from ST Microelectronics.
--
-- Design provided and tested on the Spartan-3E Starter Kit (Revision B)
--
-- Ken Chapman - Xilinx Ltd - 2nd November 2005
--
-- The JTAG loader utility is also available for rapid program development.
--
-- The design is set up for a 50MHz system clock and UART communications of 115200 baud
-- 8-bit, no parity, 1 stop-bit. IMPORTANT note: Soft flow control XON/XOFF is used.
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Furthermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The module defines some of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
--
entity SP3E1600E_PicoBlaze_spi_flash_DTE_115200_prog is
Port (
RS232_TXD : out std_logic;
RS232_RXD : in std_logic;
spi_sck : out std_logic;
spi_sdo : in std_logic;
spi_sdi : out std_logic;
spi_rom_cs : out std_logic;
spi_amp_cs : out std_logic;
spi_adc_conv : out std_logic;
spi_dac_cs : out std_logic;
spi_amp_shdn : out std_logic;
spi_amp_sdo : in std_logic;
spi_dac_clr : out std_logic;
strataflash_oe : out std_logic;
strataflash_ce : out std_logic;
strataflash_we : out std_logic;
platformflash_oe : out std_logic;
clk : in std_logic);
end SP3E1600E_PicoBlaze_spi_flash_DTE_115200_prog;
--
------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of SP3E1600E_PicoBlaze_spi_flash_DTE_115200_prog is
--
------------------------------------------------------------------------------------
--
-- declaration of KCPSM3
--
component kcpsm3
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- declaration of program ROM
--
component spi_prog
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
proc_reset : out std_logic; --JTAG Loader version
clk : in std_logic);
end component;
--
-- declaration of UART transmitter with integral 16 byte FIFO buffer
-- Note this is a modified version of the standard 'uart_tx' in which
-- the 'data_present' signal has also been brought out to better support
-- the XON/XOFF flow control.
--
component uart_tx_plus
Port ( data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end component;
--
-- declaration of UART Receiver with integral 16 byte FIFO buffer
--
component uart_rx
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM3 to program ROM and I/O logic
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic :='0';
signal interrupt_ack : std_logic;
signal kcpsm3_reset : std_logic;
--
-- Signals for connection of peripherals
--
signal status_port : std_logic_vector(7 downto 0);
--
--
-- Signals for UART connections
--
signal baud_count : integer range 0 to 26 :=0;
signal en_16_x_baud : std_logic;
signal write_to_uart : std_logic;
signal tx_data_present : std_logic;
signal tx_full : std_logic;
signal tx_half_full : std_logic;
signal read_from_uart : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_data_present : std_logic;
signal rx_full : std_logic;
signal rx_half_full : std_logic;
--
--
-- Signals used to generate interrupt
--
signal previous_rx_half_full : std_logic;
signal rx_half_full_event : std_logic;
--
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
begin
--
--
----------------------------------------------------------------------------------------------------------------------------------
-- Disable unused components
----------------------------------------------------------------------------------------------------------------------------------
--
--StrataFLASH must be disabled to prevent it driving the SDI line with its D0 output
--or conflicting with the LCD display
--
strataflash_oe <= '1';
strataflash_ce <= '1';
strataflash_we <= '1';
--
--Platform FLASH must be disabled to prevent it driving the SDI line with its D0 output.
--Since the CE is via teh 9500 device, the OE/RESET is the easier direct control (OE active high).
--
platformflash_oe <= '0';
--
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 and the program memory
----------------------------------------------------------------------------------------------------------------------------------
--
processor: kcpsm3
port map( address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -