📄 spi_prog.psm
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;
;
;
;CONSTANT SPI_control_port, pp ;SPI clock and chip selects *
;CONSTANT SPI_sck, 01 ; SCK - bit0 *
;CONSTANT SPI_rom_cs, 02 ; serial rom select - bit1 *
;CONSTANT SPI_spare_control, 04 ; spare - bit2
;CONSTANT SPI_amp_cs, 08 ; amplifier select - bit3
;CONSTANT SPI_adc_conv, 10 ; A/D convert - bit4
;CONSTANT SPI_dac_cs, 20 ; D/A select - bit5
;CONSTANT SPI_amp_shdn, 40 ; amplifier SHDN - bit6
;CONSTANT SPI_dac_clr, 80 ; D/A clear - bit7
;
;CONSTANT SPI_output_port, pp ;SPI data output *
;CONSTANT SPI_sdo, 80 ; SDO - bit7 *
;
;CONSTANT SPI_input_port, pp ;SPI data input *
;CONSTANT SPI_sdi, 80 ; SDI - bit7 *
;CONSTANT SPI_amp_sdi, 40 ; amplifier SDI - bit6
;
;
;A single scratch pad memory location is also employed to remember the status of
;the SPI_control_port. This memory location must be defined as follows.
; (replace 'ss' with appropriate memory location)
;
;CONSTANT SPI_control_status, ss ;SPI status signals
;
;Not all the SPI routines will use this memory location because although they
;will change the bits on the control port, they will leave them in the same state
;as they were in when they started.
;
;
;
;
;Initialise SPI bus
;
;This routine should be used to initialise the SPI bus.
;The SCK clock is made low.
;Device selections are made inactive as follows
; SPI_sck = 0 Clock is Low (required)
; SPI_rom_cs = 1 Deselect ROM
; spare = 1 spare control bit
; SPI_amp_cs = 1 Deselect amplifier
; SPI_adc_conv = 0 A/D convert ready to apply positive pulse
; SPI_dac_cs = 1 Deselect D/A
; SPI_amp_shdn = 0 Amplifier active and available
; SPI_dac_clr = 1 D/A clear off
;
SPI_init: LOAD s0, AE ;normally AE
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
RETURN
;
;
;Send and receive one byte to or from the SPI FLASH memory.
;
;The data supplied in register 's2' is transmitted to the SPI bus and
;at the same time any received byte is used to replace the value in 's2'.
;The SCK clock is generated by software and results in a communication rate of
;2.5Mbit/s with a 50MHz clock.
;
;Note that you must have previously selected the required device on the bus
;before attempting communication and you must subsequently deselect the device
;when appropriate.
;
;Entry to this routine assumes that SCK is already Low and the clock will be Low
;at the end of execution (provided in scratch pad memory location SPI_control_status).
;
;As a 'master' the signal sequence is as follows..
; Receive data bit from SDI line (Flash transmits on previous falling edge)
; Transmit data bit on SDO line
; Drive SCK transition from low to high
; Drive SCK transition from high to low.
;
SPI_FLASH_tx_rx: LOAD s1, 08 ;8-bits to transmit and receive
FETCH s0, SPI_control_status ;read control status bits
next_SPI_FLASH_bit: OUTPUT s2, SPI_output_port ;output data bit ready to be used on rising edge
INPUT s3, SPI_input_port ;read input bit
TEST s3, SPI_sdi ;detect state of received bit
SLA s2 ;shift new data into result and move to next transmit bit
XOR s0, SPI_sck ;clock High (bit0)
OUTPUT s0, SPI_control_port ;drive clock High
XOR s0, SPI_sck ;clock Low (bit0)
OUTPUT s0, SPI_control_port ;drive clock Low
SUB s1, 01 ;count bits
JUMP NZ, next_SPI_FLASH_bit ;repeat until finished
RETURN
;
;
;Read status register from SPI FLASH memory (ST type M25P16)
;
;Transmits instruction 05hex and then receives one byte in response
;which is returned in register s2.
;
; bit meaning
; 7 SRWD Status Register Write Protect
; 6 '0'
; 5 '0'
; 4 BP2 Block protect bit
; 3 BP1 Block protect bit
; 2 BP0 Block protect bit
; 1 WEL Write Enable Latch Bit
; 0 WIP Write In Progress
;
;
read_spi_flash_status: CALL SPI_init ;ensure known state of bus and s0 register
XOR s0, SPI_rom_cs ;select (Low) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
LOAD s2, 05 ;Read Status register instruction
CALL SPI_FLASH_tx_rx ;transmit instruction
CALL SPI_FLASH_tx_rx ;Receive status register information
XOR s0, SPI_rom_cs ;deselect (High) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
RETURN
;
;Set write enable mode in SPI FLASH memory (ST type M25P16)
;
;Transmits instruction 06hex.
;
set_spi_flash_WREN: CALL SPI_init ;ensure known state of bus and s0 register
XOR s0, SPI_rom_cs ;select (Low) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
LOAD s2, 06 ;Set write enable mode instruction
CALL SPI_FLASH_tx_rx ;transmit instruction
XOR s0, SPI_rom_cs ;deselect (High) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
RETURN
;
;Reset the write enable mode in SPI FLASH memory (ST type M25P16)
;
;Transmits instruction 04hex.
;
reset_spi_flash_WREN: CALL SPI_init ;ensure known state of bus and s0 register
XOR s0, SPI_rom_cs ;select (Low) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
LOAD s2, 04 ;Reset write enable mode instruction
CALL SPI_FLASH_tx_rx ;transmit instruction
XOR s0, SPI_rom_cs ;deselect (High) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
RETURN
;
;Read the identification ID from SPI FLASH memory (ST type M25P16)
;
;Transmits instruction 9Fhex and then reads the 3 byte response into [s9,s8,s7]
;
;response should be
; s9 = Manufacturer Identification = 20 hex
; s8 = Memory Type = 20 hex
; s7 = Memory Capacity = 15 hex
;
read_spi_flash_ID: CALL SPI_init ;ensure known state of bus and s0 register
XOR s0, SPI_rom_cs ;select (Low) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
LOAD s2, 9F ;Read ID instruction
CALL SPI_FLASH_tx_rx ;transmit instruction
CALL SPI_FLASH_tx_rx ;receive Manufacturer ID
LOAD s9, s2
CALL SPI_FLASH_tx_rx ;receive Memory Type
LOAD s8, s2
CALL SPI_FLASH_tx_rx ;receive Memory Capacity
LOAD s7, s2
XOR s0, SPI_rom_cs ;deselect (High) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
RETURN
;
;Read a single byte from the SPI FLASH memory (ST type M25P16)
;
;Transmits instruction 03hex followed by a 24-bit address which must be supplied in the
;register set [s9,s8,s7]. It then transmits a dummy byte to retrieve the memory data
;which is returned in register s2.
;
read_spi_byte: CALL SPI_init ;ensure known state of bus and s0 register
XOR s0, SPI_rom_cs ;select (Low) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
LOAD s2, 03 ;Read Data Bytes instruction
CALL SPI_FLASH_tx_rx ;transmit instruction
LOAD s2, s9 ;Transmit 24-bit address
CALL SPI_FLASH_tx_rx
LOAD s2, s8
CALL SPI_FLASH_tx_rx
LOAD s2, s7
CALL SPI_FLASH_tx_rx
CALL SPI_FLASH_tx_rx ;read data byte
XOR s0, SPI_rom_cs ;deselect (High) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
RETURN
;
;
;Erase a single sector from the SPI FLASH memory (ST type M25P16)
;
;Sets the WREN instruction and then transmits instruction D8 hex followed by a 24-bit
;address which must be supplied in the register set [s9,s8,s7]. The address must be
;at some location within the sector to be erased. A sector erase can take up to
;3 seconds to complete. The routine therefore reads the FLASH status and tests
;the write in progress (WIP) bit to test for completion
;
erase_spi_sector: CALL set_spi_flash_WREN ;set write enable mode
CALL SPI_init ;ensure known state of bus and s0 register
XOR s0, SPI_rom_cs ;select (Low) FLASH
OUTPUT s0, SPI_control_port
STORE s0, SPI_control_status ;preserve status
LOAD s2, D8 ;Sector erase mode
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