📄 progctrl.psm
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LOAD s8, 00
LOAD s7, 00
LOAD s1, 90 ;command to read device information
CALL SF_byte_write
CALL SF_byte_read ;read Device Manufacturer Code into s0
CALL send_hex_byte ;display byte
CALL send_space
LOAD s7, 02 ;change address
CALL SF_byte_read ;read Memory ID code into s0
CALL send_hex_byte ;display byte
CALL send_CR
CALL set_SF_read_array_mode ;restore normal read array mode
JUMP prompt
;
;
;**************************************************************************************
; Read StrataFLASH status register
;**************************************************************************************
;
; The main reason for reading the status register is to determine when the memory
; is ready or busy. This information is provided by bit7 (0=busy and 1=ready).
;
; The lower bits all indicate errors of some kind and therefore the only desirable
; response is 00 hex or 80 hex. In this program, no error checking or clearing
; is performed and the way this routine is executed from the menu only 80 hex is
; expected.
;
; To read the status register the read status register command must be written to
; the device. All subsequent reads are then result in the return of the status
; register. A different read command must be written to the device to stop this
; mode.
;
; This mode is also entered automatically when performing program and erase operations.
;
SF_status: LOAD s9, 00 ;define base address 000000
LOAD s8, 00
LOAD s7, 00
LOAD s1, 70 ;command to read status register
CALL SF_byte_write
CALL send_CR
CALL SF_byte_read ;read status register into s0
CALL send_hex_byte ;display byte
CALL send_CR
CALL set_SF_read_array_mode
JUMP prompt
;
;
;**************************************************************************************
; Read a byte from StrataFlash Memory
;**************************************************************************************
;
; The 24-bit address should be supplied in register set [s9,s8,s7].
; Register s0 will return the byte data retrieved from the memory.
;
; To read a byte, the address needs to be set up on the address lines
; and the controls set as follows
; SF_read = 1 - disable Spartan data outputs and enable StrataFlash outputs (OE=0)
; SF_ce = 0 - enable StrataFLASH memory
; SF_we = 1 - Write enable off
;
; The access time of the memory is 75ns. This is equivalent to 3.75 clock cycles at
; 50MHz. Since each KCPSM3 instruction takes 2 clock cycles to execute, two instructions
; provides adequate delay for the memory to be accessed.
;
; Registers used s0,s1,s7,s8,s9
;
SF_byte_read: OUTPUT s9, SF_addr_hi_port ;set 24-bit address
OUTPUT s8, SF_addr_mi_port
OUTPUT s7, SF_addr_lo_port
LOAD s1, 05 ;set controls
OUTPUT s1, SF_control_port
LOAD s1, 06 ;>75ns delay
LOAD s1, 06 ;but do something useful!
INPUT s0, SF_data_in_port ;read data byte
OUTPUT s1, SF_control_port ;clear controls
RETURN
;
;
;**************************************************************************************
; Write data or command byte to StrataFlash Memory
;**************************************************************************************
;
; The 24-bit address should be supplied in register set [s9,s8,s7].
; Register s1 should contain the byte to be written to the memory.
;
; To write a byte, the address needs to be set up on the address lines
; and the controls set as follows
; SF_read = 0 - enable Spartan data outputs and disable StrataFlash outputs (OE=1)
; SF_ce = 0 - enable StrataFLASH memory
; SF_we = 0 - Write enable on
;
; The setup time of the memory is 60ns. This is equivalent to 3 clock cycles at
; 50MHz. Since each KCPSM3 instruction takes 2 clock cycles to execute, two instructions
; provides adequate delay for the memory.
;
; Registers used s1,s7,s8,s9
;
SF_byte_write: OUTPUT s9, SF_addr_hi_port ;set 24-bit address
OUTPUT s8, SF_addr_mi_port
OUTPUT s7, SF_addr_lo_port
OUTPUT s1, SF_data_out_port ;set data byte to be written
LOAD s1, 00 ;set controls
OUTPUT s1, SF_control_port
LOAD s1, 06 ;>60ns delay
LOAD s1, 06 ;but do something useful!
OUTPUT s1, SF_control_port ;clear controls
RETURN
;
;
;**************************************************************************************
; Set 'Read Array' mode on StrataFLASH
;**************************************************************************************
;
; The read array mode is the default mode of the memory and allows the contents
; of the memory to be read based on the supplied address.
;
; Read array is the default mode of the device, but it must also be placed back
; into this mode after programming, erasing or reading the status register.
;
; The read array command (FF hex) is written to the Strata flash memory.
;
; Registers used s1,s7,s8,s9
;
set_SF_read_array_mode: LOAD s1, FF ;command to read array
CALL SF_byte_write
RETURN
;
;
;**************************************************************************************
; Wait for StrataFLASH to be ready
;**************************************************************************************
;
; This routine will typically be used after instigating a program or erase
; command. It continuously reads the StrataFLASH status register and tests the
; information provided by bit7 which indicates if the memory is busy(0) or ready(1).
; The routine waits for the ready condition before sending a read array command
; which puts the memory back to normal read mode.
;
; During the polling process, a counter formed by register pair [sE,sD] records
; approximately how long the memory is busy. This can be used to evaluate programming
; and erase times if required. The timing loop is 15 instructions which is equivalent
; to 30 clock cycles (600ns at 50MHz)
;
; Registers used s0,s1,s7,s8,s9,sD,sE (s7,s8,s9 not changed)
;
;
wait_SF_ready: LOAD sE, 00 ;clear 16-bit counter timer
LOAD sD, 00
wait_SF_loop: ADD sD, 01 ;increment counter timer
ADDCY sE, 00
CALL SF_byte_read ;read status register into s0
TEST s0, 80 ;test ready/busy flag
JUMP Z, wait_SF_loop
CALL set_SF_read_array_mode ;restore normal read array mode
RETURN
;
;
;**************************************************************************************
; Send 16-bit value in register pair [sE,sD] to UART
;**************************************************************************************
;
; In this program the register pair [sE,sD] indicates the programming time of the
; StrataFLASH memory in 600ns increments. This routine can be used to display that
; value if required.
;
send_counter_timer: CALL send_CR
LOAD s0, sE
CALL send_hex_byte
LOAD s0, sD
CALL send_hex_byte
CALL send_CR
RETURN
;
;
;**************************************************************************************
;Software delay routines
;**************************************************************************************
;
;Delay of 1us.
;
;Constant value defines reflects the clock applied to KCPSM3. Every instruction
;executes in 2 clock cycles making the calculation highly predictable. The '6' in
;the following equation even allows for 'CALL delay_1us' instruction in the initiating code.
;
; delay_1us_constant = (clock_rate - 6)/4 Where 'clock_rate' is in MHz
;
;Registers used s0
;
delay_1us: LOAD s0, delay_1us_constant
wait_1us: SUB s0, 01
JUMP NZ, wait_1us
RETURN
;
;Delay of 40us.
;
;Registers used s0, s1
;
delay_40us: LOAD s1, 28 ;40 x 1us = 40us
wait_40us: CALL delay_1us
SUB s1, 01
JUMP NZ, wait_40us
RETURN
;
;
;Delay of 1ms.
;
;Registers used s0, s1, s2
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