progctrl.vhd

利用picoblaze微控制器对Intel flash进行控制

               INIT_17 => X"D030B8000181102003060306030603061300B80001811030A000016710700167",
               INIT_18 => X"002213000022A000800AA000C0F6B80080075D8BC011B800C0E9B80080B9A000",
               INIT_19 => X"0F6301310F6901310F5001930193A00001310F20A00001310F0DA00001741200",
               INIT_1A => X"01310F4E019601310F6501310F7A01310F6101310F6C01310F4201310F6F0131",
               INIT_1B => X"019601310F4801310F5301310F4101310F4C01310F46019601310F5201310F4F",
               INIT_1C => X"01310F6D01310F6D01310F6101310F7201310F6701310F6F01310F7201310F50",
               INIT_1D => X"019301310F3001310F3001310F2E01310F3101310F76019601310F7201310F65",
               INIT_1E => X"01310F6701310F6E01310F6901310F7401310F6901310F6101310F57A0000193",
               INIT_1F => X"0F46019601310F5301310F4301310F4D019601310F7201310F6F01310F660196",
               INIT_20 => X"0F50019601310F6E01310F690220A000019301310F6501310F6C01310F690131",
               INIT_21 => X"A0000193013101310F7301310F6501310F7201310F6701310F6F01310F720131",
               INIT_22 => X"0F4B01310F4F0193A000019601310F6501310F7301310F6101310F7201310F45",
               INIT_23 => X"0F420193013101310F6C01310F61022001310F2D01310F450193A00001930131",
               INIT_24 => X"01310F7301310F6B01310F6301310F6F01310F6C01310F62022001310F2D0131",
               INIT_25 => X"01310F7201310F5001310F2D01310F50019301310F3301310F2D01310F310196",
               INIT_26 => X"0F5701310F2D01310F5701F701310F6D01310F6101310F7201310F6701310F6F",
               INIT_27 => X"01310F2D01310F52019302CB019601310F6501310F7401310F6901310F720131",
               INIT_28 => X"019601310F3601310F3501310F32019601310F6401310F6101310F6501310F52",
               INIT_29 => X"01310F6901310F7601310F6501310F4401310F2D01310F49019301310F7302CB",
               INIT_2A => X"0F6C01310F6501310F4801310F2D01310F48019302C6019601310F6501310F63",
               INIT_2B => X"01310F7401310F6101310F7401310F5301310F2D01310F53019301310F700131",
               INIT_2C => X"0F7401310F7901310F62A00001310F4401310F49A000019301310F7301310F75",
               INIT_2D => X"0F7201310F6901310F6601310F6E01310F6F01310F430193A00001310F650131",
               INIT_2E => X"019601310F2901310F6E01310F2F01310F5901310F280220019601310F6D0131",
               INIT_2F => X"0F610193A000019301310F7401310F7201310F6F01310F6201310F410193A000",
               INIT_30 => X"0F640193A00001310F3D013101310F7301310F6501310F72013101310F640131",
               INIT_31 => X"00000000000000000000000000000000430B01310F6101310F7401310F610131",
               INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
               INIT_3F => X"43F580016000C004001143FC001353FB20104000E00000000000000000000000",    
               INITP_00 => X"34DF2118674436CC99F73CFD9FFFEF33FF7C0FF7FCCA2CFFF3DDDDDDDDF3FFFF",
               INITP_01 => X"BDD42CA08AAA022AFFFC03FF3FC03CFBDDD5F3F3FCF3CFEF33FFF3CF3FBCD55C",
               INITP_02 => X"2CAA2CB332CCE5D8C0EA89B19A2C998999752BD3D3D2F4F4EDCB72DCB72D2F33",
               INITP_03 => X"3CCCF333CCCCCCCBF33333CCCCCCCCCCF33333CCCF333333333ECB2CCE667666",
               INITP_04 => X"CCFF3333333CCCCCCCCCF333CCCCCCF33F33CCEF33BCCCCCBF3333333CCEF333",
               INITP_05 => X"3BCCCCCEF33333F3333333B3332CCBCCCCCCCCF333333FCCCCCCCCF3F333CCCC",
               INITP_06 => X"0000000000000000000000000000000000000000000000000000F3333B3CCCF3",
               INITP_07 => X"F233480000000000000000000000000000000000000000000000000000000000")
  --synthesis translate_on
  port map(    DIB => "0000000000000000",
              DIPB => "00",
               ENB => '1',
               WEB => '0',
              SSRB => '0',
              CLKB => clk,
             ADDRB => address,
               DOB => instruction(15 downto 0),
              DOPB => instruction(17 downto 16),
               DIA => jdata,
              DIPA => jparity,
               ENA => sel1,
               WEA => '1',
              SSRA => '0',
              CLKA => update,
              ADDRA=> jaddr,
               DOA => doa(7 downto 0),
              DOPA => dopa); 
  v2_bscan: BSCAN_VIRTEX2 
  port map(   TDO1 => tdo1,
         TDO2 => tdo2,
            UPDATE => update,
             SHIFT => shift,
             RESET => reset,
               TDI => tdi,
              SEL1 => sel1,
             DRCK1 => drck1,
              SEL2 => sel2,
             DRCK2 => drck2,
      CAPTURE => capture);
  --buffer signal used as a clock
  upload_clock: BUFG
  port map( I => drck1,
            O => drck1_buf);
  -- Assign the reset to be active whenever the uploading subsystem is active
  proc_reset <= sel1;
  srlC1: SRLC16E
  --synthesis translate_off
  generic map (INIT => X"0000")
  --synthesis translate_on
  port map(   D => tdi,
             CE => '1',
            CLK => drck1_buf,
             A0 => '1',
             A1 => '0',
             A2 => '1',
             A3 => '1',
              Q => jaddr(10),
            Q15 => jaddr(8));
  flop1: FD
  port map ( D => jaddr(10),
             Q => jaddr(9),
             C => drck1_buf);
  srlC2: SRLC16E
  --synthesis translate_off
  generic map (INIT => X"0000")
  --synthesis translate_on
  port map(   D => jaddr(8),
             CE => '1',
            CLK => drck1_buf,
             A0 => '1',
             A1 => '0',
             A2 => '1',
             A3 => '1',
              Q => jaddr(7),
            Q15 => tap5);
  flop2: FD
  port map ( D => jaddr(7),
             Q => jaddr(6),
             C => drck1_buf);
  srlC3: SRLC16E
  --synthesis translate_off
  generic map (INIT => X"0000")
  --synthesis translate_on
  port map(   D => tap5,
             CE => '1',
            CLK => drck1_buf,
             A0 => '1',
             A1 => '0',
             A2 => '1',
             A3 => '1',
              Q => jaddr(5),
            Q15 => jaddr(3));
  flop3: FD
  port map ( D => jaddr(5),
             Q => jaddr(4),
             C => drck1_buf);
  srlC4: SRLC16E
  --synthesis translate_off
  generic map (INIT => X"0000")
  --synthesis translate_on
  port map(   D => jaddr(3),
             CE => '1',
            CLK => drck1_buf,
             A0 => '1',
             A1 => '0',
             A2 => '1',
             A3 => '1',
              Q => jaddr(2),
            Q15 => tap11);
  flop4: FD
  port map ( D => jaddr(2),
             Q => jaddr(1),
             C => drck1_buf);
  srlC5: SRLC16E
  --synthesis translate_off
  generic map (INIT => X"0000")
  --synthesis translate_on
  port map(   D => tap11,
             CE => '1',
            CLK => drck1_buf,
             A0 => '1',
             A1 => '0',
             A2 => '1',
             A3 => '1',
              Q => jaddr(0),
            Q15 => jdata(7));
  flop5: FD
  port map ( D => jaddr(0),
             Q => jparity(0),
             C => drck1_buf);
  srlC6: SRLC16E
  --synthesis translate_off
  generic map (INIT => X"0000")
  --synthesis translate_on
  port map(   D => jdata(7),
             CE => '1',
            CLK => drck1_buf,
             A0 => '1',
             A1 => '0',
             A2 => '1',
             A3 => '1',
              Q => jdata(6),
            Q15 => tap17);
  flop6: FD
  port map ( D => jdata(6),
             Q => jdata(5),
             C => drck1_buf);
  srlC7: SRLC16E
  --synthesis translate_off
  generic map (INIT => X"0000")
  --synthesis translate_on
  port map(   D => tap17,
             CE => '1',
            CLK => drck1_buf,
             A0 => '1',
             A1 => '0',
             A2 => '1',
             A3 => '1',
              Q => jdata(4),
            Q15 => jdata(2));
  flop7: FD
  port map ( D => jdata(4),
             Q => jdata(3),
             C => drck1_buf);
  srlC8: SRLC16E
  --synthesis translate_off
  generic map (INIT => X"0000")
  --synthesis translate_on
  port map(   D => jdata(2),
             CE => '1',
            CLK => drck1_buf,
             A0 => '1',
             A1 => '0',
             A2 => '1',
             A3 => '1',
              Q => jdata(1),
            Q15 => tdo1);
  flop8: FD
  port map ( D => jdata(1),
             Q => jdata(0),
             C => drck1_buf);
end low_level_definition;
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