downcnt.vhd

来自「倒数计数器」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;

entity downcnt is
generic(modulus:integer:=8);           --定义modulus为整型常量，值为8
port(clock:in std_logic;
	e:in std_logic;
	l:in std_logic;
	q:out integer range 0 to modulus-1);
end downcnt;

architecture behavior of downcnt is
	signal count:integer range 0 to modulus-1;
begin
	process
	begin
		wait until clock'event and clock='1';
		if e='1' then 
			if l='1' then count<=modulus-1;
			else count<=count-1;
		 	end if;
		end if;
	end process;
	q<=count;
end behavior;
--为了使加，减，乘，除4种运算电路均能在相同的时间内完成运算。
--当e='1'时，计数器才会计数，当l='1'时，计数器赋初始值。