hanmin.tan.qmsg

4位汉明编译码源代码。VHDL格式

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 02 13:12:17 2006 " "Info: Processing started: Sat Dec 02 13:12:17 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off hanmin -c hanmin " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off hanmin -c hanmin" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "din\[0\] cdout\[1\] 7.153 ns Longest " "Info: Longest tpd from source pin \"din\[0\]\" to destination pin \"cdout\[1\]\" is 7.153 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns din\[0\] 1 PIN PIN_69 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_69; Fanout = 5; PIN Node = 'din\[0\]'" {  } { { "F:/hanmin/db/hanmin_cmp.qrpt" "" { Report "F:/hanmin/db/hanmin_cmp.qrpt" Compiler "hanmin" "UNKNOWN" "V1" "F:/hanmin/db/hanmin.quartus_db" { Floorplan "F:/hanmin/" "" "" { din[0] } "NODE_NAME" } "" } } { "hanmin.bdf" "" { Schematic "F:/hanmin/hanmin.bdf" { { 88 -24 144 104 "din\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.576 ns) + CELL(0.511 ns) 4.219 ns hanmin_cd:inst\|hamout\[6\] 2 COMB LC_X5_Y4_N1 1 " "Info: 2: + IC(2.576 ns) + CELL(0.511 ns) = 4.219 ns; Loc. = LC_X5_Y4_N1; Fanout = 1; COMB Node = 'hanmin_cd:inst\|hamout\[6\]'" {  } { { "F:/hanmin/db/hanmin_cmp.qrpt" "" { Report "F:/hanmin/db/hanmin_cmp.qrpt" Compiler "hanmin" "UNKNOWN" "V1" "F:/hanmin/db/hanmin.quartus_db" { Floorplan "F:/hanmin/" "" "3.087 ns" { din[0] hanmin_cd:inst|hamout[6] } "NODE_NAME" } "" } } { "hanmin_cd.vhd" "" { Text "F:/hanmin/hanmin_cd.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.612 ns) + CELL(2.322 ns) 7.153 ns cdout\[1\] 3 PIN PIN_87 0 " "Info: 3: + IC(0.612 ns) + CELL(2.322 ns) = 7.153 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'cdout\[1\]'" {  } { { "F:/hanmin/db/hanmin_cmp.qrpt" "" { Report "F:/hanmin/db/hanmin_cmp.qrpt" Compiler "hanmin" "UNKNOWN" "V1" "F:/hanmin/db/hanmin.quartus_db" { Floorplan "F:/hanmin/" "" "2.934 ns" { hanmin_cd:inst|hamout[6] cdout[1] } "NODE_NAME" } "" } } { "hanmin.bdf" "" { Schematic "F:/hanmin/hanmin.bdf" { { 88 464 640 104 "cdout\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.965 ns 55.43 % " "Info: Total cell delay = 3.965 ns ( 55.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.188 ns 44.57 % " "Info: Total interconnect delay = 3.188 ns ( 44.57 % )" {  } {  } 0}  } { { "F:/hanmin/db/hanmin_cmp.qrpt" "" { Report "F:/hanmin/db/hanmin_cmp.qrpt" Compiler "hanmin" "UNKNOWN" "V1" "F:/hanmin/db/hanmin.quartus_db" { Floorplan "F:/hanmin/" "" "7.153 ns" { din[0] hanmin_cd:inst|hamout[6] cdout[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "7.153 ns" { din[0] din[0]~combout hanmin_cd:inst|hamout[6] cdout[1] } { 0.000ns 0.000ns 2.576ns 0.612ns } { 0.000ns 1.132ns 0.511ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 02 13:12:17 2006 " "Info: Processing ended: Sat Dec 02 13:12:17 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}