hanmin.map.qmsg

4位汉明编译码源代码。VHDL格式

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 02 13:12:04 2006 " "Info: Processing started: Sat Dec 02 13:12:04 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off hanmin -c hanmin " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hanmin -c hanmin" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hanmin_cd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file hanmin_cd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hanmin_cd-ver2 " "Info: Found design unit 1: hanmin_cd-ver2" {  } { { "hanmin_cd.vhd" "" { Text "F:/hanmin/hanmin_cd.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 hanmin_cd " "Info: Found entity 1: hanmin_cd" {  } { { "hanmin_cd.vhd" "" { Text "F:/hanmin/hanmin_cd.vhd" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hanmin_de.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file hanmin_de.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hanmin_de-ver1 " "Info: Found design unit 1: hanmin_de-ver1" {  } { { "hanmin_de.vhd" "" { Text "F:/hanmin/hanmin_de.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 hanmin_de " "Info: Found entity 1: hanmin_de" {  } { { "hanmin_de.vhd" "" { Text "F:/hanmin/hanmin_de.vhd" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hanmin.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file hanmin.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 hanmin " "Info: Found entity 1: hanmin" {  } { { "hanmin.bdf" "" { Schematic "F:/hanmin/hanmin.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "hanmin " "Info: Elaborating entity \"hanmin\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hanmin_de hanmin_de:inst1 " "Info: Elaborating entity \"hanmin_de\" for hierarchy \"hanmin_de:inst1\"" {  } { { "hanmin.bdf" "inst1" { Schematic "F:/hanmin/hanmin.bdf" { { 248 240 408 376 "inst1" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ne hanmin_de.vhd(19) " "Warning: VHDL Process Statement warning at hanmin_de.vhd(19): signal or variable \"ne\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ne\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "hanmin_de.vhd" "" { Text "F:/hanmin/hanmin_de.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ded hanmin_de.vhd(19) " "Warning: VHDL Process Statement warning at hanmin_de.vhd(19): signal or variable \"ded\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ded\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "hanmin_de.vhd" "" { Text "F:/hanmin/hanmin_de.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "sec hanmin_de.vhd(19) " "Warning: VHDL Process Statement warning at hanmin_de.vhd(19): signal or variable \"sec\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"sec\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "hanmin_de.vhd" "" { Text "F:/hanmin/hanmin_de.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dataout hanmin_de.vhd(19) " "Warning: VHDL Process Statement warning at hanmin_de.vhd(19): signal or variable \"dataout\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"dataout\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "hanmin_de.vhd" "" { Text "F:/hanmin/hanmin_de.vhd" 19 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hanmin_cd hanmin_cd:inst " "Info: Elaborating entity \"hanmin_cd\" for hierarchy \"hanmin_cd:inst\"" {  } { { "hanmin.bdf" "inst" { Schematic "F:/hanmin/hanmin.bdf" { { 64 240 408 160 "inst" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "hanmin_de:inst1\|dataout\[0\] " "Warning: LATCH primitive \"hanmin_de:inst1\|dataout\[0\]\" is permanently enabled" {  } { { "hanmin_de.vhd" "" { Text "F:/hanmin/hanmin_de.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "hanmin_de:inst1\|dataout\[1\] " "Warning: LATCH primitive \"hanmin_de:inst1\|dataout\[1\]\" is permanently enabled" {  } { { "hanmin_de.vhd" "" { Text "F:/hanmin/hanmin_de.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "hanmin_de:inst1\|dataout\[2\] " "Warning: LATCH primitive \"hanmin_de:inst1\|dataout\[2\]\" is permanently enabled" {  } { { "hanmin_de.vhd" "" { Text "F:/hanmin/hanmin_de.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "hanmin_de:inst1\|dataout\[3\] " "Warning: LATCH primitive \"hanmin_de:inst1\|dataout\[3\]\" is permanently enabled" {  } { { "hanmin_de.vhd" "" { Text "F:/hanmin/hanmin_de.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "sec GND " "Warning: Pin \"sec\" stuck at GND" {  } { { "hanmin.bdf" "" { Schematic "F:/hanmin/hanmin.bdf" { { 288 464 640 304 "sec" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ded GND " "Warning: Pin \"ded\" stuck at GND" {  } { { "hanmin.bdf" "" { Schematic "F:/hanmin/hanmin.bdf" { { 304 464 640 320 "ded" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ne VCC " "Warning: Pin \"ne\" stuck at VCC" {  } { { "hanmin.bdf" "" { Schematic "F:/hanmin/hanmin.bdf" { { 320 464 640 336 "ne" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "23 " "Info: Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "4 " "Info: Implemented 4 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 02 13:12:07 2006 " "Info: Processing ended: Sat Dec 02 13:12:07 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}