hanmin.map.rpt

4位汉明编译码源代码。VHDL格式

; hanmin_cd.vhd                    ; yes             ; User VHDL File                     ; F:/hanmin/hanmin_cd.vhd      ;
; hanmin_de.vhd                    ; yes             ; User VHDL File                     ; F:/hanmin/hanmin_de.vhd      ;
; hanmin.bdf                       ; yes             ; User Block Diagram/Schematic File  ; F:/hanmin/hanmin.bdf         ;
+----------------------------------+-----------------+------------------------------------+------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 4         ;
; Total combinational functions   ; 4         ;
;     -- Total 4-input functions  ; 0         ;
;     -- Total 3-input functions  ; 4         ;
;     -- Total 2-input functions  ; 0         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 0         ;
; I/O pins                        ; 19        ;
; Maximum fan-out node            ; din[3]    ;
; Maximum fan-out                 ; 5         ;
; Total fan-out                   ; 24        ;
; Average fan-out                 ; 1.04      ;
+---------------------------------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name    ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
; |hanmin                    ; 4 (0)       ; 0            ; 0          ; 19   ; 0            ; 4 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |hanmin                ;
;    |hanmin_cd:inst|        ; 4 (4)       ; 0            ; 0          ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |hanmin|hanmin_cd:inst ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |hanmin|hanmin_de:inst1|process0~5 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/hanmin/hanmin.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Dec 02 13:12:04 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hanmin -c hanmin
Info: Found 2 design units, including 1 entities, in source file hanmin_cd.vhd
    Info: Found design unit 1: hanmin_cd-ver2
    Info: Found entity 1: hanmin_cd
Info: Found 2 design units, including 1 entities, in source file hanmin_de.vhd
    Info: Found design unit 1: hanmin_de-ver1
    Info: Found entity 1: hanmin_de
Info: Found 1 design units, including 1 entities, in source file hanmin.bdf
    Info: Found entity 1: hanmin
Info: Elaborating entity "hanmin" for the top level hierarchy
Info: Elaborating entity "hanmin_de" for hierarchy "hanmin_de:inst1"
Warning: VHDL Process Statement warning at hanmin_de.vhd(19): signal or variable "ne" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ne" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at hanmin_de.vhd(19): signal or variable "ded" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "ded" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at hanmin_de.vhd(19): signal or variable "sec" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sec" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at hanmin_de.vhd(19): signal or variable "dataout" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "dataout" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "hanmin_cd" for hierarchy "hanmin_cd:inst"
Warning: LATCH primitive "hanmin_de:inst1|dataout[0]" is permanently enabled
Warning: LATCH primitive "hanmin_de:inst1|dataout[1]" is permanently enabled
Warning: LATCH primitive "hanmin_de:inst1|dataout[2]" is permanently enabled
Warning: LATCH primitive "hanmin_de:inst1|dataout[3]" is permanently enabled
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "sec" stuck at GND
    Warning: Pin "ded" stuck at GND
    Warning: Pin "ne" stuck at VCC
Info: Implemented 23 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 15 output pins
    Info: Implemented 4 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Processing ended: Sat Dec 02 13:12:07 2006
    Info: Elapsed time: 00:00:04