📄 hanmin.fit.rpt
字号:
; sec ; Output ; -- ;
; ded ; Output ; -- ;
; ne ; Output ; -- ;
; cdout[7] ; Output ; -- ;
; cdout[6] ; Output ; -- ;
; cdout[5] ; Output ; -- ;
; cdout[4] ; Output ; -- ;
; cdout[3] ; Output ; -- ;
; cdout[2] ; Output ; -- ;
; cdout[1] ; Output ; -- ;
; cdout[0] ; Output ; -- ;
; dout[3] ; Output ; -- ;
; dout[2] ; Output ; -- ;
; dout[1] ; Output ; -- ;
; dout[0] ; Output ; -- ;
+----------+----------+---------------+
+------------------------------------+
; Non-Global High Fan-Out Signals ;
+--------------------------+---------+
; Name ; Fan-Out ;
+--------------------------+---------+
; din[0] ; 5 ;
; din[1] ; 5 ;
; din[2] ; 5 ;
; din[3] ; 5 ;
; hanmin_cd:inst|hamout[7] ; 1 ;
; hanmin_cd:inst|hamout[6] ; 1 ;
; hanmin_cd:inst|hamout[5] ; 1 ;
; hanmin_cd:inst|hamout[4] ; 1 ;
+--------------------------+---------+
+------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-------------------+
; C4s ; 4 / 784 ( < 1 % ) ;
; Direct links ; 0 / 888 ( 0 % ) ;
; Global clocks ; 0 / 4 ( 0 % ) ;
; LAB clocks ; 0 / 32 ( 0 % ) ;
; LUT chains ; 0 / 216 ( 0 % ) ;
; Local interconnects ; 16 / 888 ( 1 % ) ;
; R4s ; 12 / 704 ( 1 % ) ;
+----------------------------+-------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 1.33) ; Number of LABs (Total = 3) ;
+--------------------------------------------+-----------------------------+
; 1 ; 2 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
+--------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 1.33) ; Number of LABs (Total = 3) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 1.33) ; Number of LABs (Total = 3) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 3.33) ; Number of LABs (Total = 3) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Dec 02 13:12:09 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off hanmin -c hanmin
Info: Selected device EPM240T100C5 for design "hanmin"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: No exact pin location assignment(s) for 19 pins of 19 total pins
Info: Pin sec not assigned to an exact location on the device
Info: Pin ded not assigned to an exact location on the device
Info: Pin ne not assigned to an exact location on the device
Info: Pin cdout[7] not assigned to an exact location on the device
Info: Pin cdout[6] not assigned to an exact location on the device
Info: Pin cdout[5] not assigned to an exact location on the device
Info: Pin cdout[4] not assigned to an exact location on the device
Info: Pin cdout[3] not assigned to an exact location on the device
Info: Pin cdout[2] not assigned to an exact location on the device
Info: Pin cdout[1] not assigned to an exact location on the device
Info: Pin cdout[0] not assigned to an exact location on the device
Info: Pin dout[3] not assigned to an exact location on the device
Info: Pin dout[2] not assigned to an exact location on the device
Info: Pin dout[1] not assigned to an exact location on the device
Info: Pin dout[0] not assigned to an exact location on the device
Info: Pin din[3] not assigned to an exact location on the device
Info: Pin din[2] not assigned to an exact location on the device
Info: Pin din[1] not assigned to an exact location on the device
Info: Pin din[0] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 19 (unused VREF, 3.30 VCCIO, 4 input, 15 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 38 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is pin to pin delay of 7.234 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_6; Fanout = 5; PIN Node = 'din[3]'
Info: 2: + IC(2.289 ns) + CELL(0.914 ns) = 4.335 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'hanmin_cd:inst|hamout[6]'
Info: 3: + IC(0.577 ns) + CELL(2.322 ns) = 7.234 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'cdout[1]'
Info: Total cell delay = 4.368 ns ( 60.38 % )
Info: Total interconnect delay = 2.866 ns ( 39.62 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Dec 02 13:12:12 2006
Info: Elapsed time: 00:00:04
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