fpga.c

一个调整ADC gain offset 的程序

#include "extData.h"
#include "define.h"
#include "fpga.h"
#include "dvIIC.h"
#include "stdio.h"
#include "intrins.h"

//FPGA
volatile BYTE xdata CNTLGain       _at_ 0x07E0;
volatile BYTE xdata ReadyAlert     _at_ 0x07E7;
volatile BYTE xdata TestFPGA       _at_ 0x07E9;
volatile BYTE xdata GainRealTime   _at_ 0x07E3;
volatile BYTE xdata OffsetRealTime _at_ 0x07E4;

BYTE xdata ADCGainRef     	_at_ 0x07E1;
BYTE xdata ADCGainRef_h    	_at_ 0x07F1;
BYTE xdata ADCOffsetRef   	_at_ 0x07E2;
BYTE xdata ADCOffsetRef_h  	_at_ 0x07F2;
BYTE xdata Selector       	_at_ 0x07E5;
BYTE xdata BlankThresh    	_at_ 0x07E6;
BYTE xdata DisplayLED     	_at_ 0x07E8;
BYTE xdata SerialPort       _at_ 0x07EC;
BYTE xdata FPGALED     		_at_ 0x07ed;
BYTE xdata DelaySet     	_at_ 0x07eb;  //HM added,06/11/23
// changed by holy 061118 for reg added
BYTE xdata VBlank     		_at_ 0x07ee;
BYTE xdata ADCDelayL   		_at_ 0x07ef;
BYTE xdata ADCDelayH		_at_ 0x07f0;
// changed by holy 061215 for reg added
BYTE xdata TestSignal		_at_ 0x07f5;
BYTE xdata RealTimeH		_at_ 0x07f4;
 BYTE cData;
 
BOOL InitFPGA(void)
{

  BOOL bTemp =TRUE;
  #ifdef DATABUS
  
  TestFPGA = 0x55;
  //Delay();
  BlankThresh    = 0x20; 
 // Delay();
  cData = TestFPGA;
  DelaySet =0x0b; //HM added,06/11/23
 // Delay();
  #endif
  
   #ifdef IIC
    dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xe9,0x55);
    dvRegisterRead(IIC_FPGA_SLAVE_Addr, 0xe9,&cData);
    dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xe6,0x5c);
    dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xeb,0x0b); //HM added,06/11/23
   #endif
   
  if(cData== 0xaa)
  {
    bTemp=TRUE;
  }
  else
  {
    bTemp=FALSE;
  }
  
  return bTemp;
}

void  FPGABoardClear(BYTE CSelBoard)
{
    #ifdef IIC
    if(CSelBoard==0)
   	       dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe7,0x03,1);
  else 
   	    dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe7,0x03,2);
 #endif
 
  #ifdef DATABUS
   if(CSelBoard==0)
    	{
    	      cData = ReadyAlert;
    	     // Delay();
    	      cData&=0xfc;
    	      ReadyAlert = cData+0x01;
    	      //Delay();
    	 }
  else 
  	{
    	      cData = ReadyAlert;
    	     // Delay();
    	      cData&=0xfc;
    	      ReadyAlert = cData+0x02;
    	      //Delay();
  	}
  Delay();
  Delay();
  Delay();
  #endif
}

void  FPGABoardSelect(BYTE CSelBoard)
{
    #ifdef IIC
    if(CSelBoard==0)
    	{
   	        dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe5,0x10,0);
   	        //dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe7,0x01,1);
    	 }
  else
  	{
           
   	    dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe5,0x10,1);
   	   // dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe7,0x02,1);
  	}
  	
 #endif
 
  #ifdef DATABUS
   if(CSelBoard==0)
    	{
    	      cData = Selector;
    	     // Delay();
    	      cData&=0xef;
    	      Selector =  cData;
    	     // Delay();
    	     /* cData = ReadyAlert;
    	      cData&=0xfe;
    	      ReadyAlert = cData+0x01;
    	      */
    	 }
  else
  	{
            cData = Selector;
            //Delay();
    	      cData&=0xef;
    	      Selector =  cData+0x10;
    	   //   Delay();
    	     /* cData = ReadyAlert;
    	      cData&=0xfd;
    	      ReadyAlert = cData+0x02;*/
  	}
  #endif
}
void GxBoardSelect(BYTE CSelBoard)
{
   #ifdef IIC
    dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe5,0x0c,CSelBoard);
   #endif

    #ifdef DATABUS
     cData =Selector ;
  //  Delay();
      cData&=0xf3;
      Selector=  cData+ (CSelBoard<<2);
    //  Delay();
  #endif
}


void RGBChannelSelect(BYTE CSelChannel)
{
    #ifdef IIC
   dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe5,0x03,CSelChannel);
    #endif
   #ifdef DATABUS
    cData =Selector ;
   //Delay();
     cData&=0xfc;
      Selector=  cData+CSelChannel;
  //    Delay();
  #endif
}

void InputFormatSelect(BYTE CSelFormat)
{
  if(CSelFormat ==0)
     	{
          #ifdef INPUT_480I_SOY
           CSelFormat =0;
          #endif
          #ifdef INPUT_480I_SYNC
            CSelFormat =2;
          #endif
     	}
  if(CSelFormat ==1)
  	CSelFormat=5;
    #ifdef IIC
     dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe5,0xe0,CSelFormat);
    #endif

   #ifdef DATABUS
       cData =Selector ;
    //  Delay();
       cData&=0x1f;
      Selector=  cData+(CSelFormat<<5);
     // Delay();
  #endif
}
void RefGainSet(WORD wGain)
{
  #ifdef IIC
   dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xe1,LoByte(wGain));
    dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xf1,HiByte(wGain));
    #endif
     #ifdef DATABUS
    ADCGainRef = LoByte(wGain);
    ADCGainRef_h = HiByte(wGain);
    // Delay();
  #endif
}
/*
void H_RefGainSet(BYTE cGain)
{
  #ifdef IIC
   dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xf1,cGain);
    #endif
     #ifdef DATABUS
    ADCGainRef_h = cGain;
    // Delay();
  #endif
}
*/
void RefOffsetSet(WORD wOffset)
{

#ifdef IIC
   dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xe2,LoByte(wOffset));
  dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xf2,HiByte(wOffset));
    #endif
     #ifdef DATABUS
	 ADCOffsetRef = LoByte(wOffset);
       ADCOffsetRef_h = HiByte(wOffset);
  //   Delay();
  #endif
}

void TestSignalSet(BYTE cValue)
{
#ifdef IIC  
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xf5, 0x01, cValue);
#endif
#ifdef DATABUS	
	TestSignal= cValue;
#endif	
}
WORD RefOffsetGet()
{
 WORD wOffset;
  BYTE cValueL,cValueH;
 #ifdef IIC
   dvRegisterRead(IIC_FPGA_SLAVE_Addr, 0xe4,cValueL);
  dvRegisterRead(IIC_FPGA_SLAVE_Addr, 0xf4,cValueH);
  #endif
     #ifdef DATABUS
	 cValueL=OffsetRealTime ;
        cValueH=RealTimeH;
  #endif
   wOffset = cValueL+((cValueH&0x03)<<8);
  return wOffset;
}

/*
void H_RefOffsetSet(BYTE cOffset)
{

#ifdef IIC
   dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xf2,cOffset);
    #endif
     #ifdef DATABUS
	 ADCOffsetRef_h = cOffset;
  //   Delay();
  #endif
}
*/
void GxBoardLEDSet(BYTE GXBoardSel,BYTE cStatus)
{
  
   #ifdef IIC
   dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe8, 3<<(6-GXBoardSel*2), cStatus);
   #endif
    #ifdef DATABUS
     cData = DisplayLED;
 //   Delay();
     cData&=   ~(3<<(6-GXBoardSel*2));
    DisplayLED=cData+(cStatus<<(6-GXBoardSel*2));
 //   Delay();
   #endif
}
void FPGABoardLEDSet(BYTE cLEDSel,BOOL bStatus)	
{
  #ifdef IIC
   dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xed, 1<<cLEDSel, bStatus);
  #endif
  #ifdef DATABUS 
  cData=FPGALED;
//  Delay();
   cData&=~(1<<cLEDSel);
   FPGALED=cData+ (((BYTE)bStatus)<<cLEDSel);
//    Delay();
  #endif
}
#if 0
// changed by holy 061118 for reg added
void InputFormatParaSet(BYTE CSelFormat)
{
	if(CSelFormat ==0)
 	{
#ifdef INPUT_480I_SOY
#ifdef IIC
		dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xee,0xff,0x32);
		dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xef,0xff,0x80);
#endif

#ifdef DATABUS
		VBlank = 0x32;
		ADCDelayL= 0x80;
#endif
#endif
	}
}
#endif
void Delay()
{
    _nop_ ();
    _nop_ ();
     _nop_ ();
     _nop_ ();
       _nop_ ();
    _nop_ ();
     _nop_ ();
     _nop_ ();
      _nop_ ();
     _nop_ ();
    
}