📄 fpga.lst
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C51 COMPILER V7.50 FPGA 01/17/2007 12:46:58 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE FPGA
OBJECT MODULE PLACED IN .\output\fpga.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE ..\code\fpga.c LARGE BROWSE DEBUG OBJECTEXTEND PRINT(.\fpga.lst) OBJECT(.\o
-utput\fpga.obj)
line level source
1 #include "extData.h"
2 #include "define.h"
3 #include "fpga.h"
4 #include "dvIIC.h"
5 #include "stdio.h"
6 #include "intrins.h"
7
8 //FPGA
9 volatile BYTE xdata CNTLGain _at_ 0x07E0;
10 volatile BYTE xdata ReadyAlert _at_ 0x07E7;
11 volatile BYTE xdata TestFPGA _at_ 0x07E9;
12 volatile BYTE xdata GainRealTime _at_ 0x07E3;
13 volatile BYTE xdata OffsetRealTime _at_ 0x07E4;
14
15 BYTE xdata ADCGainRef _at_ 0x07E1;
16 BYTE xdata ADCGainRef_h _at_ 0x07F1;
17 BYTE xdata ADCOffsetRef _at_ 0x07E2;
18 BYTE xdata ADCOffsetRef_h _at_ 0x07F2;
19 BYTE xdata Selector _at_ 0x07E5;
20 BYTE xdata BlankThresh _at_ 0x07E6;
21 BYTE xdata DisplayLED _at_ 0x07E8;
22 BYTE xdata SerialPort _at_ 0x07EC;
23 BYTE xdata FPGALED _at_ 0x07ed;
24 BYTE xdata DelaySet _at_ 0x07eb; //HM added,06/11/23
25 // changed by holy 061118 for reg added
26 BYTE xdata VBlank _at_ 0x07ee;
27 BYTE xdata ADCDelayL _at_ 0x07ef;
28 BYTE xdata ADCDelayH _at_ 0x07f0;
29 // changed by holy 061215 for reg added
30 BYTE xdata TestSignal _at_ 0x07f5;
31 BYTE xdata RealTimeH _at_ 0x07f4;
32 BYTE cData;
33
34 BOOL InitFPGA(void)
35 {
36 1
37 1 BOOL bTemp =TRUE;
38 1 #ifdef DATABUS
39 1
40 1 TestFPGA = 0x55;
41 1 //Delay();
42 1 BlankThresh = 0x20;
43 1 // Delay();
44 1 cData = TestFPGA;
45 1 DelaySet =0x0b; //HM added,06/11/23
46 1 // Delay();
47 1 #endif
48 1
49 1 #ifdef IIC
dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xe9,0x55);
dvRegisterRead(IIC_FPGA_SLAVE_Addr, 0xe9,&cData);
dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xe6,0x5c);
dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xeb,0x0b); //HM added,06/11/23
#endif
C51 COMPILER V7.50 FPGA 01/17/2007 12:46:58 PAGE 2
55 1
56 1 if(cData== 0xaa)
57 1 {
58 2 bTemp=TRUE;
59 2 }
60 1 else
61 1 {
62 2 bTemp=FALSE;
63 2 }
64 1
65 1 return bTemp;
66 1 }
67
68 void FPGABoardClear(BYTE CSelBoard)
69 {
70 1 #ifdef IIC
if(CSelBoard==0)
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe7,0x03,1);
else
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe7,0x03,2);
#endif
76 1
77 1 #ifdef DATABUS
78 1 if(CSelBoard==0)
79 1 {
80 2 cData = ReadyAlert;
81 2 // Delay();
82 2 cData&=0xfc;
83 2 ReadyAlert = cData+0x01;
84 2 //Delay();
85 2 }
86 1 else
87 1 {
88 2 cData = ReadyAlert;
89 2 // Delay();
90 2 cData&=0xfc;
91 2 ReadyAlert = cData+0x02;
92 2 //Delay();
93 2 }
94 1 Delay();
95 1 Delay();
96 1 Delay();
97 1 #endif
98 1 }
99
100 void FPGABoardSelect(BYTE CSelBoard)
101 {
102 1 #ifdef IIC
if(CSelBoard==0)
{
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe5,0x10,0);
//dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe7,0x01,1);
}
else
{
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe5,0x10,1);
// dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe7,0x02,1);
}
#endif
116 1
C51 COMPILER V7.50 FPGA 01/17/2007 12:46:58 PAGE 3
117 1 #ifdef DATABUS
118 1 if(CSelBoard==0)
119 1 {
120 2 cData = Selector;
121 2 // Delay();
122 2 cData&=0xef;
123 2 Selector = cData;
124 2 // Delay();
125 2 /* cData = ReadyAlert;
126 2 cData&=0xfe;
127 2 ReadyAlert = cData+0x01;
128 2 */
129 2 }
130 1 else
131 1 {
132 2 cData = Selector;
133 2 //Delay();
134 2 cData&=0xef;
135 2 Selector = cData+0x10;
136 2 // Delay();
137 2 /* cData = ReadyAlert;
138 2 cData&=0xfd;
139 2 ReadyAlert = cData+0x02;*/
140 2 }
141 1 #endif
142 1 }
143 void GxBoardSelect(BYTE CSelBoard)
144 {
145 1 #ifdef IIC
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe5,0x0c,CSelBoard);
#endif
148 1
149 1 #ifdef DATABUS
150 1 cData =Selector ;
151 1 // Delay();
152 1 cData&=0xf3;
153 1 Selector= cData+ (CSelBoard<<2);
154 1 // Delay();
155 1 #endif
156 1 }
157
158
159 void RGBChannelSelect(BYTE CSelChannel)
160 {
161 1 #ifdef IIC
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe5,0x03,CSelChannel);
#endif
164 1 #ifdef DATABUS
165 1 cData =Selector ;
166 1 //Delay();
167 1 cData&=0xfc;
168 1 Selector= cData+CSelChannel;
169 1 // Delay();
170 1 #endif
171 1 }
172
173 void InputFormatSelect(BYTE CSelFormat)
174 {
175 1 if(CSelFormat ==0)
176 1 {
177 2 #ifdef INPUT_480I_SOY
CSelFormat =0;
C51 COMPILER V7.50 FPGA 01/17/2007 12:46:58 PAGE 4
#endif
180 2 #ifdef INPUT_480I_SYNC
181 2 CSelFormat =2;
182 2 #endif
183 2 }
184 1 if(CSelFormat ==1)
185 1 CSelFormat=5;
186 1 #ifdef IIC
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe5,0xe0,CSelFormat);
#endif
189 1
190 1 #ifdef DATABUS
191 1 cData =Selector ;
192 1 // Delay();
193 1 cData&=0x1f;
194 1 Selector= cData+(CSelFormat<<5);
195 1 // Delay();
196 1 #endif
197 1 }
198 void RefGainSet(WORD wGain)
199 {
200 1 #ifdef IIC
dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xe1,LoByte(wGain));
dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xf1,HiByte(wGain));
#endif
204 1 #ifdef DATABUS
205 1 ADCGainRef = LoByte(wGain);
206 1 ADCGainRef_h = HiByte(wGain);
207 1 // Delay();
208 1 #endif
209 1 }
210 /*
211 void H_RefGainSet(BYTE cGain)
212 {
213 #ifdef IIC
214 dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xf1,cGain);
215 #endif
216 #ifdef DATABUS
217 ADCGainRef_h = cGain;
218 // Delay();
219 #endif
220 }
221 */
222 void RefOffsetSet(WORD wOffset)
223 {
224 1
225 1 #ifdef IIC
dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xe2,LoByte(wOffset));
dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xf2,HiByte(wOffset));
#endif
229 1 #ifdef DATABUS
230 1 ADCOffsetRef = LoByte(wOffset);
231 1 ADCOffsetRef_h = HiByte(wOffset);
232 1 // Delay();
233 1 #endif
234 1 }
235
236 void TestSignalSet(BYTE cValue)
237 {
238 1 #ifdef IIC
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xf5, 0x01, cValue);
#endif
C51 COMPILER V7.50 FPGA 01/17/2007 12:46:58 PAGE 5
241 1 #ifdef DATABUS
242 1 TestSignal= cValue;
243 1 #endif
244 1 }
245 WORD RefOffsetGet()
246 {
247 1 WORD wOffset;
248 1 BYTE cValueL,cValueH;
249 1 #ifdef IIC
dvRegisterRead(IIC_FPGA_SLAVE_Addr, 0xe4,cValueL);
dvRegisterRead(IIC_FPGA_SLAVE_Addr, 0xf4,cValueH);
#endif
253 1 #ifdef DATABUS
254 1 cValueL=OffsetRealTime ;
255 1 cValueH=RealTimeH;
256 1 #endif
257 1 wOffset = cValueL+((cValueH&0x03)<<8);
258 1 return wOffset;
259 1 }
260
261 /*
262 void H_RefOffsetSet(BYTE cOffset)
263 {
264
265 #ifdef IIC
266 dvRegisterWrite(IIC_FPGA_SLAVE_Addr, 0xf2,cOffset);
267 #endif
268 #ifdef DATABUS
269 ADCOffsetRef_h = cOffset;
270 // Delay();
271 #endif
272 }
273 */
274 void GxBoardLEDSet(BYTE GXBoardSel,BYTE cStatus)
275 {
276 1
277 1 #ifdef IIC
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xe8, 3<<(6-GXBoardSel*2), cStatus);
#endif
280 1 #ifdef DATABUS
281 1 cData = DisplayLED;
282 1 // Delay();
283 1 cData&= ~(3<<(6-GXBoardSel*2));
284 1 DisplayLED=cData+(cStatus<<(6-GXBoardSel*2));
285 1 // Delay();
286 1 #endif
287 1 }
288 void FPGABoardLEDSet(BYTE cLEDSel,BOOL bStatus)
289 {
290 1 #ifdef IIC
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xed, 1<<cLEDSel, bStatus);
#endif
293 1 #ifdef DATABUS
294 1 cData=FPGALED;
295 1 // Delay();
296 1 cData&=~(1<<cLEDSel);
297 1 FPGALED=cData+ (((BYTE)bStatus)<<cLEDSel);
298 1 // Delay();
299 1 #endif
300 1 }
301 #if 0
// changed by holy 061118 for reg added
C51 COMPILER V7.50 FPGA 01/17/2007 12:46:58 PAGE 6
void InputFormatParaSet(BYTE CSelFormat)
{
if(CSelFormat ==0)
{
#ifdef INPUT_480I_SOY
#ifdef IIC
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xee,0xff,0x32);
dvRegisterMaskWrite(IIC_FPGA_SLAVE_Addr, 0xef,0xff,0x80);
#endif
#ifdef DATABUS
VBlank = 0x32;
ADCDelayL= 0x80;
#endif
#endif
}
}
#endif
321 void Delay()
322 {
323 1 _nop_ ();
324 1 _nop_ ();
325 1 _nop_ ();
326 1 _nop_ ();
327 1 _nop_ ();
328 1 _nop_ ();
329 1 _nop_ ();
330 1 _nop_ ();
331 1 _nop_ ();
332 1 _nop_ ();
333 1
334 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 352 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = 1 ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- 2
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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