📄 mtv415.m51
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BL51 BANKED LINKER/LOCATER V5.12 01/17/2007 18:30:24 PAGE 1
BL51 BANKED LINKER/LOCATER V5.12, INVOKED BY:
C:\KEIL\C51\BIN\BL51.EXE .\output\STARTUP.obj, .\output\utility.obj, .\output\dvCPU.obj, .\output\dvIIC.obj, .\output\ee
>> prom.obj, .\output\main.obj, .\output\fpga.obj, .\output\dvGxCtrl.obj TO .\output\mtv415 PRINT (.\mtv415.m51) RAMSIZE
>> (256) CODE (0X0000-0X9FFF) XDATA (0X0800-0X087F, 0X0900-0X097F, 0X0E00-0X0E7F)
MEMORY MODEL: LARGE
INPUT MODULES INCLUDED:
.\output\STARTUP.obj (?C_STARTUP)
.\output\utility.obj (UTILITY)
.\output\dvCPU.obj (DVCPU)
.\output\dvIIC.obj (DVIIC)
.\output\eeprom.obj (EEPROM)
.\output\main.obj (MAIN)
.\output\fpga.obj (FPGA)
.\output\dvGxCtrl.obj (DVGXCTRL)
C:\KEIL\C51\LIB\C51L.LIB (?C_INIT)
C:\KEIL\C51\LIB\C51L.LIB (?C?CLDOPTR)
C:\KEIL\C51\LIB\C51L.LIB (?C?CSTPTR)
C:\KEIL\C51\LIB\C51L.LIB (?C?CSTOPTR)
C:\KEIL\C51\LIB\C51L.LIB (?C?IMUL)
C:\KEIL\C51\LIB\C51L.LIB (?C?UIDIV)
C:\KEIL\C51\LIB\C51L.LIB (?C?IILDX)
C:\KEIL\C51\LIB\C51L.LIB (PRINTF)
C:\KEIL\C51\LIB\C51L.LIB (?C?CLDPTR)
C:\KEIL\C51\LIB\C51L.LIB (?C?PLDIXDATA)
C:\KEIL\C51\LIB\C51L.LIB (?C?PSTXDATA)
C:\KEIL\C51\LIB\C51L.LIB (?C?CCASE)
LINK MAP OF MODULE: .\output\mtv415 (?C_STARTUP)
TYPE BASE LENGTH RELOCATION SEGMENT NAME
-----------------------------------------------------
* * * * * * * D A T A M E M O R Y * * * * * * *
REG 0000H 0008H ABSOLUTE "REG BANK 0"
DATA 0008H 0005H UNIT _DATA_GROUP_
000DH 0013H *** GAP ***
BIT 0020H.0 0001H.4 UNIT _BIT_GROUP_
BIT 0021H.4 0000H.2 UNIT ?BI?DVIIC
0021H.6 0000H.2 *** GAP ***
IDATA 0022H 0001H UNIT ?STACK
* * * * * * * X D A T A M E M O R Y * * * * * * *
0000H 07E0H *** GAP ***
XDATA 07E0H 0001H ABSOLUTE
XDATA 07E1H 0001H ABSOLUTE
XDATA 07E2H 0001H ABSOLUTE
XDATA 07E3H 0001H ABSOLUTE
XDATA 07E4H 0001H ABSOLUTE
XDATA 07E5H 0001H ABSOLUTE
XDATA 07E6H 0001H ABSOLUTE
XDATA 07E7H 0001H ABSOLUTE
XDATA 07E8H 0001H ABSOLUTE
BL51 BANKED LINKER/LOCATER V5.12 01/17/2007 18:30:24 PAGE 2
XDATA 07E9H 0001H ABSOLUTE
07EAH 0001H *** GAP ***
XDATA 07EBH 0001H ABSOLUTE
XDATA 07ECH 0001H ABSOLUTE
XDATA 07EDH 0001H ABSOLUTE
XDATA 07EEH 0001H ABSOLUTE
XDATA 07EFH 0001H ABSOLUTE
XDATA 07F0H 0001H ABSOLUTE
XDATA 07F1H 0001H ABSOLUTE
XDATA 07F2H 0001H ABSOLUTE
07F3H 0001H *** GAP ***
XDATA 07F4H 0001H ABSOLUTE
XDATA 07F5H 0001H ABSOLUTE
07F6H 000AH *** GAP ***
XDATA 0800H 0039H UNIT _XDATA_GROUP_
XDATA 0839H 0032H UNIT ?XD?EEPROM
XDATA 086BH 0009H UNIT ?XD?DVGXCTRL
XDATA 0874H 0004H UNIT ?XD?UTILITY
XDATA 0878H 0001H UNIT ?XD?DVIIC
XDATA 0879H 0001H UNIT ?XD?FPGA
087AH 0686H *** GAP ***
XDATA 0F00H 0001H ABSOLUTE
XDATA 0F01H 0001H ABSOLUTE
0F02H 0001H *** GAP ***
XDATA 0F03H 0001H ABSOLUTE
XDATA 0F04H 0001H ABSOLUTE
XDATA 0F05H 0001H ABSOLUTE
XDATA 0F06H 0001H ABSOLUTE
XDATA 0F07H 0001H ABSOLUTE
XDATA 0F08H 0001H ABSOLUTE
XDATA 0F09H 0001H ABSOLUTE
XDATA 0F0AH 0001H ABSOLUTE
XDATA 0F0BH 0001H ABSOLUTE
XDATA 0F0CH 0001H ABSOLUTE
XDATA 0F0DH 0001H ABSOLUTE
XDATA 0F0EH 0001H ABSOLUTE
XDATA 0F0FH 0001H ABSOLUTE
XDATA 0F10H 0001H ABSOLUTE
XDATA 0F11H 0001H ABSOLUTE
XDATA 0F12H 0001H ABSOLUTE
XDATA 0F13H 0001H ABSOLUTE
0F14H 0004H *** GAP ***
XDATA 0F18H 0001H ABSOLUTE
0F19H 0007H *** GAP ***
XDATA 0F20H 0001H ABSOLUTE
XDATA 0F21H 0001H ABSOLUTE
XDATA 0F22H 0001H ABSOLUTE
XDATA 0F23H 0001H ABSOLUTE
0F24H 0009H *** GAP ***
XDATA 0F2DH 0001H ABSOLUTE
XDATA 0F2EH 0001H ABSOLUTE
XDATA 0F2FH 0001H ABSOLUTE
0F30H 0008H *** GAP ***
XDATA 0F38H 0001H ABSOLUTE
XDATA 0F39H 0001H ABSOLUTE
XDATA 0F3AH 0001H ABSOLUTE
XDATA 0F3BH 0001H ABSOLUTE
BL51 BANKED LINKER/LOCATER V5.12 01/17/2007 18:30:24 PAGE 3
XDATA 0F3CH 0001H ABSOLUTE
XDATA 0F3DH 0001H ABSOLUTE
XDATA 0F3EH 0001H ABSOLUTE
XDATA 0F3FH 0001H ABSOLUTE
0F40H 0008H *** GAP ***
XDATA 0F48H 0001H ABSOLUTE
XDATA 0F49H 0001H ABSOLUTE
0F4AH 0006H *** GAP ***
XDATA 0F50H 0001H ABSOLUTE
XDATA 0F51H 0001H ABSOLUTE
XDATA 0F52H 0001H ABSOLUTE
XDATA 0F53H 0001H ABSOLUTE
XDATA 0F54H 0001H ABSOLUTE
XDATA 0F55H 0001H ABSOLUTE
XDATA 0F56H 0001H ABSOLUTE
XDATA 0F57H 0001H ABSOLUTE
XDATA 0F58H 0001H ABSOLUTE
XDATA 0F59H 0001H ABSOLUTE
XDATA 0F5AH 0001H ABSOLUTE
XDATA 0F5BH 0001H ABSOLUTE
XDATA 0F5CH 0001H ABSOLUTE
XDATA 0F5DH 0001H ABSOLUTE
0F5EH 0023H *** GAP ***
XDATA 0F81H 0001H ABSOLUTE
XDATA 0F82H 0001H ABSOLUTE
0F83H 0003H *** GAP ***
XDATA 0F86H 0001H ABSOLUTE
XDATA 0F87H 0001H ABSOLUTE
XDATA 0F88H 0001H ABSOLUTE
XDATA 0F89H 0001H ABSOLUTE
XDATA 0F8AH 0001H ABSOLUTE
XDATA 0F8BH 0001H ABSOLUTE
XDATA 0F8CH 0001H ABSOLUTE
XDATA 0F8DH 0001H ABSOLUTE
XDATA 0F8EH 0001H ABSOLUTE
0F8FH 0002H *** GAP ***
XDATA 0F91H 0001H ABSOLUTE
0F92H 0001H *** GAP ***
XDATA 0F93H 0001H ABSOLUTE
XDATA 0F94H 0001H ABSOLUTE
0F95H 0003H *** GAP ***
XDATA 0F98H 0001H ABSOLUTE
XDATA 0F99H 0001H ABSOLUTE
XDATA 0F9AH 0001H ABSOLUTE
* * * * * * * C O D E M E M O R Y * * * * * * *
CODE 0000H 0003H ABSOLUTE
CODE 0003H 0007H UNIT ?PR?INITTIMER0?DVCPU
000AH 0001H *** GAP ***
CODE 000BH 0003H ABSOLUTE
CODE 000EH 0365H UNIT ?PR?PRINTF?PRINTF
CODE 0373H 02E8H UNIT ?CO?DVGXCTRL
CODE 065BH 02AEH UNIT ?PR?MAIN?MAIN
CODE 0909H 022BH UNIT ?PR?_E2PROMDATASET?EEPROM
CODE 0B34H 019BH UNIT ?PR?_EEPROMUOCSETTINGGET?EEPROM
CODE 0CCFH 0172H UNIT ?PR?_GXEEPROMWRITE?EEPROM
CODE 0E41H 0161H UNIT ?CO?MAIN
BL51 BANKED LINKER/LOCATER V5.12 01/17/2007 18:30:24 PAGE 4
CODE 0FA2H 015CH UNIT ?PR?_CALIBRATIONPROCESS?MAIN
CODE 10FEH 0153H UNIT ?PR?_GXINITIAL?DVGXCTRL
CODE 1251H 013DH UNIT ?C?LIB_CODE
CODE 138EH 0107H UNIT ?PR?_IICREAD?DVIIC
CODE 1495H 00DDH UNIT ?CO?EEPROM
CODE 1572H 00ABH UNIT ?PR?_IICWRITE?DVIIC
CODE 161DH 008CH UNIT ?C_C51STARTUP
CODE 16A9H 0075H UNIT ?PR?_DVREGISTERMASKWRITE?DVIIC
CODE 171EH 0069H UNIT ?PR?_GXOFFSETGET?DVGXCTRL
CODE 1787H 0066H UNIT ?PR?_GXOFFSETSET?DVGXCTRL
CODE 17EDH 005DH UNIT ?PR?TIMER0?DVCPU
CODE 184AH 0050H UNIT ?PR?_GXGAINGET?DVGXCTRL
CODE 189AH 0045H UNIT ?C_INITSEG
CODE 18DFH 003CH UNIT ?PR?_E2PROMDATAGET?EEPROM
CODE 191BH 003BH UNIT ?PR?DVCPUINIT?DVCPU
CODE 1956H 0039H UNIT ?PR?IICACKWAIT?DVIIC
CODE 198FH 0036H UNIT ?PR?_GXBOARDLEDSET?FPGA
CODE 19C5H 002FH UNIT ?PR?_FPGABOARDLEDSET?FPGA
CODE 19F4H 002FH UNIT ?PR?_GXGAINSET?DVGXCTRL
CODE 1A23H 002DH UNIT ?PR?_PUTCHAR?DVCPU
CODE 1A50H 002CH UNIT ?PR?INITFPGA?FPGA
CODE 1A7CH 002CH UNIT ?PR?GXADCTESTSET?DVGXCTRL
CODE 1AA8H 002AH UNIT ?PR?_FPGABOARDCLEAR?FPGA
CODE 1AD2H 0029H UNIT ?PR?INITSERIALPORT?DVCPU
CODE 1AFBH 0022H UNIT ?PR?_INPUTFORMATSELECT?FPGA
CODE 1B1DH 001FH UNIT ?PR?_FPGABOARDSELECT?FPGA
CODE 1B3CH 001AH UNIT ?PR?_DVREGISTERWRITE?DVIIC
CODE 1B56H 0019H UNIT ?PR?CALIBRATIONTIMERPROCESS?UTILITY
CODE 1B6FH 0017H UNIT ?PR?_GXBOARDSELECT?FPGA
CODE 1B86H 0015H UNIT ?PR?REFOFFSETGET?FPGA
CODE 1B9BH 0013H UNIT ?PR?_TIMEDELAY?UTILITY
CODE 1BAEH 0011H UNIT ?PR?_RGBCHANNELSELECT?FPGA
CODE 1BBFH 000CH UNIT ?PR?INITIIC?DVCPU
CODE 1BCBH 000BH UNIT ?PR?_SHORTDELAY?EEPROM
CODE 1BD6H 000BH UNIT ?PR?_REFGAINSET?FPGA
CODE 1BE1H 000BH UNIT ?PR?_REFOFFSETSET?FPGA
CODE 1BECH 000BH UNIT ?PR?DELAY?FPGA
CODE 1BF7H 0009H UNIT ?PR?IICTIMERPROCESS?DVIIC
CODE 1C00H 0006H UNIT ?PR?INITWATCHDOG?DVCPU
CODE 1C06H 0006H UNIT ?PR?_TESTSIGNALSET?FPGA
OVERLAY MAP OF MODULE: .\output\mtv415 (?C_STARTUP)
SEGMENT BIT_GROUP DATA_GROUP XDATA_GROUP
+--> CALLED SEGMENT START LENGTH START LENGTH START LENGTH
---------------------------------------------------------------------------------------------------
?C_C51STARTUP ----- ----- ----- ----- ----- -----
+--> ?PR?MAIN?MAIN
+--> ?C_INITSEG
?PR?MAIN?MAIN 0020H.0 0000H.1 ----- ----- 0800H 0008H
+--> ?PR?DVCPUINIT?DVCPU
+--> ?CO?MAIN
+--> ?PR?PRINTF?PRINTF
BL51 BANKED LINKER/LOCATER V5.12 01/17/2007 18:30:24 PAGE 5
+--> ?PR?_TIMEDELAY?UTILITY
+--> ?PR?INITFPGA?FPGA
+--> ?PR?_FPGABOARDLEDSET?FPGA
+--> ?PR?_FPGABOARDCLEAR?FPGA
+--> ?PR?_FPGABOARDSELECT?FPGA
+--> ?PR?_GXBOARDLEDSET?FPGA
+--> ?PR?_GXBOARDSELECT?FPGA
+--> ?PR?GXADCTESTSET?DVGXCTRL
+--> ?PR?_TESTSIGNALSET?FPGA
+--> ?PR?_INPUTFORMATSELECT?FPGA
+--> ?PR?_GXINITIAL?DVGXCTRL
+--> ?PR?_EEPROMUOCSETTINGGET?EEPROM
+--> ?PR?_RGBCHANNELSELECT?FPGA
+--> ?PR?_GXGAINSET?DVGXCTRL
+--> ?PR?REFOFFSETGET?FPGA
+--> ?PR?_REFGAINSET?FPGA
+--> ?PR?_REFOFFSETSET?FPGA
+--> ?PR?_CALIBRATIONPROCESS?MAIN
+--> ?PR?_GXEEPROMWRITE?EEPROM
?PR?DVCPUINIT?DVCPU ----- ----- ----- ----- ----- -----
+--> ?PR?INITSERIALPORT?DVCPU
+--> ?PR?INITTIMER0?DVCPU
+--> ?PR?INITIIC?DVCPU
+--> ?PR?INITWATCHDOG?DVCPU
?PR?PRINTF?PRINTF 0020H.3 0001H.1 0008H 0005H 080FH 0028H
+--> ?PR?_PUTCHAR?DVCPU
?PR?_PUTCHAR?DVCPU ----- ----- ----- ----- 0837H 0002H
?PR?INITFPGA?FPGA 0020H.1 0000H.1 ----- ----- ----- -----
?PR?_FPGABOARDLEDSET?FPGA 0020H.1 0000H.1 ----- ----- ----- -----
?PR?_FPGABOARDCLEAR?FPGA ----- ----- ----- ----- ----- -----
+--> ?PR?DELAY?FPGA
?PR?GXADCTESTSET?DVGXCTRL ----- ----- ----- ----- ----- -----
+--> ?PR?_DVREGISTERMASKWRITE?DVIIC
?PR?_DVREGISTERMASKWRITE?DVIIC ----- ----- ----- ----- 0811H 0006H
+--> ?PR?_IICREAD?DVIIC
+--> ?PR?_IICWRITE?DVIIC
?PR?_IICREAD?DVIIC 0020H.3 0000H.1 0008H 0002H 0817H 0007H
+--> ?PR?IICACKWAIT?DVIIC
?PR?_IICWRITE?DVIIC 0020H.3 0000H.1 0008H 0003H 0820H 0008H
+--> ?PR?IICACKWAIT?DVIIC
?PR?_GXINITIAL?DVGXCTRL ----- ----- ----- ----- 0808H 0003H
+--> ?CO?DVGXCTRL
+--> ?PR?_DVREGISTERWRITE?DVIIC
+--> ?PR?_GXGAINGET?DVGXCTRL
+--> ?PR?_GXOFFSETGET?DVGXCTRL
BL51 BANKED LINKER/LOCATER V5.12 01/17/2007 18:30:24 PAGE 6
?PR?_DVREGISTERWRITE?DVIIC ----- ----- ----- ----- 0811H 0001H
+--> ?PR?_IICWRITE?DVIIC
?PR?_GXGAINGET?DVGXCTRL ----- ----- ----- ----- 080BH 0002H
+--> ?CO?DVGXCTRL
+--> ?PR?_GXGAINSET?DVGXCTRL
?PR?_GXGAINSET?DVGXCTRL ----- ----- ----- ----- 080FH 0001H
+--> ?PR?_DVREGISTERWRITE?DVIIC
?PR?_GXOFFSETGET?DVGXCTRL ----- ----- ----- ----- 080BH 0002H
+--> ?CO?DVGXCTRL
+--> ?PR?_GXOFFSETSET?DVGXCTRL
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