decode.v

来自「modelsim工程」· Verilog 代码 · 共 89 行

module decode(clk,rst,codein,codeoutv,codeoutb);
input clk,rst;
input codein;
output [1:0] codeoutv;
output [1:0] codeoutb;

reg [2:0] count0;
reg [2:0] count01;
reg [4:0] count11;
reg [1:0] codeoutv,codeoutb,codeout;
reg [1:0] s0,s1,s2;

reg [1:0] cnt01,cnt11;

always @ (negedge rst or posedge clk) 
 begin
  if (!rst) begin
    codeoutv<=2'b00;
    count0<=0; 
    count11<=0; end
  else begin
    if (codein==1) begin
       count0<=0;
       codeoutv<=2'b01; end
    else begin
       count0<=count0+1;
       if(count0<3)  
           codeoutv<=2'b00;
       else begin
           count0<=0;
           codeoutv<=2'b11; 
           count11<=count11+1; end
      end
   end
 end

always @ (negedge rst or posedge clk)
  begin
    if(!rst)
      count01<=0;
    else begin
        if ((count11>0)&&(codeoutv==2'b01))
           count01<=count01+1;
        else if((count11>0)&&(codeoutv==2'b11))
           count01<=0;
        else
           count01<=count01;
    end
end

always @ (posedge clk)
  begin  s0<=codeoutv; end
always @ (posedge clk)
  begin  s1<=s0; end
always @ (posedge clk)
  begin  s2<=s1; end

always @ (posedge clk)
  begin
      if((count11>1)&&(count01[0]==0)&&(codeoutv)==2'b11)
         codeoutb<=2'b10;
      else
         codeoutb<=s2;
  end
  
always @ (negedge rst or posedge clk)
  begin
    if (!rst) begin
        cnt01<=0;
        cnt11<=0; end
    else begin 
        if ((codeoutb==2'b01)||(codeoutb==2'b10)) begin
            cnt01=cnt01+1;
            if(cnt01[0]==0) codeout<=2'b01;
            else codeout<=2'b11;  end
        else if (codeoutb==2'b11) begin
            cnt11=cnt11+1;
            if(cnt11[0]==0) codeout<=2'b11;
            else codeout <= 2'b01; end    
        else begin
            codeout<=2'b00;
            cnt01<=cnt01;
            cnt11<=cnt11; end
        end
    end
    

endmodule