first.vhd

4人抢答器的硬件描述语言设计

library ieee;
use ieee.std_logic_1164.all;

entity first is
PORT(reset:in std_logic;
	a : in std_logic_vector(3 downto 0);
	lockout : out std_logic;
       firstman:out std_logic_vector(2 downto 0));

end;
architecture behavioral of first is
signal clk,lock : std_logic;
signal  c: std_logic_vector(3 downto 0);

begin
clk<='1' when a(3)='1' or a(2)='1' or a(1)='1' or a(0)='1' else '0';
lockout<=lock;
process_label:
PROCESS (clk)
BEGIN
IF reset='1'  THEN
    c<="0000";
	lock<='0';
ELSIF clk'event and clk='1' THEN
    if lock='0' then c<=a; lock<='1'; end if;
END IF;
END PROCESS process_label;
firstman<= "001" when c="1000" else
			"010" when c="0100" else
			"011" when c="0010" else
			"100" when c="0001" else
			"000";
end behavioral;