📄 light.rpt
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-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:231|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = LCELL( _EQ059);
_EQ059 = _LC5_A13
# _LC2_B18
# _LC3_A14;
-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:231|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = LCELL( _EQ060);
_EQ060 = _LC2_A22
# !_LC1_A15
# _LC3_A20;
-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:231|addcore:adder|:150' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ061);
_EQ061 = !_LC2_B18 & _LC3_A14 & !_LC5_A13
# !_LC3_A14 & _LC5_A13
# _LC2_B18 & !_LC3_A14;
-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:231|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = LCELL( _EQ062);
_EQ062 = _LC1_A16 & !_LC3_A16 & !_LC4_A16
# !_LC1_A16 & _LC3_A16
# !_LC1_A16 & _LC4_A16;
-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:470|addcore:adder|pcarry5~1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_A9', type is buried
-- synthesized logic cell
_LC3_A9 = LCELL( _EQ063);
_EQ063 = _LC7_A8
# _LC4_A7
# _LC8_A8;
-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:470|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A9', type is buried
_LC4_A9 = LCELL( _EQ064);
_EQ064 = _LC1_B12 & _LC3_A10 & _LC5_A7
# _LC3_A9;
-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:470|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_A9', type is buried
_LC5_A9 = LCELL( _EQ065);
_EQ065 = _LC1_A9 & !_LC2_A9 & !_LC4_A9
# !_LC1_A9 & _LC2_A9
# !_LC1_A9 & _LC4_A9;
-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:511|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = LCELL( _EQ066);
_EQ066 = _LC3_A10
# _LC1_B12
# _LC5_A7;
-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:511|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_A9', type is buried
_LC8_A9 = LCELL( _EQ067);
_EQ067 = _LC7_A8
# !_LC2_A12
# _LC8_A8;
-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:511|addcore:adder|:150' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_A7', type is buried
_LC3_A7 = LCELL( _EQ068);
_EQ068 = !_LC1_B12 & !_LC3_A10 & _LC5_A7
# _LC3_A10 & !_LC5_A7
# _LC1_B12 & !_LC5_A7;
-- Node name is '|LEDSHOW:26|LPM_ADD_SUB:511|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_A9', type is buried
_LC7_A9 = LCELL( _EQ069);
_EQ069 = _LC1_A9 & !_LC2_A9 & !_LC8_A9
# !_LC1_A9 & _LC2_A9
# !_LC1_A9 & _LC8_A9;
-- Node name is '|LEDSHOW:26|:8'
-- Equation name is '_LC3_B4', type is buried
_LC3_B4 = DFFE( _EQ070, _LC2_C5, VCC, VCC, VCC);
_EQ070 = urgen
# _LC2_C9;
-- Node name is '|LEDSHOW:26|:10'
-- Equation name is '_LC7_B12', type is buried
_LC7_B12 = DFFE( _EQ071, _LC2_C5, VCC, VCC, VCC);
_EQ071 = !_LC2_C9 & !_LC2_C12 & !urgen;
-- Node name is '|LEDSHOW:26|:12'
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = DFFE( _EQ072, _LC2_C5, VCC, VCC, VCC);
_EQ072 = !_LC2_C9 & _LC2_C12 & !urgen;
-- Node name is '|LEDSHOW:26|:14'
-- Equation name is '_LC2_C19', type is buried
_LC2_C19 = DFFE( _EQ073, _LC2_C5, VCC, VCC, VCC);
_EQ073 = urgen
# !_LC2_C9;
-- Node name is '|LEDSHOW:26|:16'
-- Equation name is '_LC1_C17', type is buried
_LC1_C17 = DFFE( _EQ074, _LC2_C5, VCC, VCC, VCC);
_EQ074 = _LC2_C9 & !_LC2_C12 & !urgen;
-- Node name is '|LEDSHOW:26|:18'
-- Equation name is '_LC1_C19', type is buried
_LC1_C19 = DFFE( _EQ075, _LC2_C5, VCC, VCC, VCC);
_EQ075 = _LC2_C9 & _LC2_C12 & !urgen;
-- Node name is '|LEDSHOW:26|:129'
-- Equation name is '_LC1_A15', type is buried
!_LC1_A15 = _LC1_A15~NOT;
_LC1_A15~NOT = LCELL( _EQ076);
_EQ076 = _LC4_A14
# _LC3_A14
# _LC5_A13
# _LC2_B18;
-- Node name is '|LEDSHOW:26|:269'
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = LCELL( _EQ077);
_EQ077 = !_LC1_A15 & _LC3_A16 & _LC4_A16
# !_LC1_A15 & !_LC3_A16 & !_LC4_A16
# _LC1_A15 & _LC3_A16 & _LC6_A16
# _LC1_A15 & !_LC3_A16 & !_LC6_A16;
-- Node name is '|LEDSHOW:26|:409'
-- Equation name is '_LC2_A12', type is buried
!_LC2_A12 = _LC2_A12~NOT;
_LC2_A12~NOT = LCELL( _EQ078);
_EQ078 = _LC4_A7
# _LC5_A7
# _LC3_A10
# _LC1_B12;
-- Node name is '|LEDSHOW:26|:549'
-- Equation name is '_LC6_A9', type is buried
_LC6_A9 = LCELL( _EQ079);
_EQ079 = _LC2_A9 & !_LC2_A12 & _LC8_A9
# !_LC2_A9 & !_LC2_A12 & !_LC8_A9
# _LC2_A9 & _LC2_A12 & _LC4_A9
# !_LC2_A9 & _LC2_A12 & !_LC4_A9;
-- Node name is '|LEDSHOW:26|:648'
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ080);
_EQ080 = !clk & urgen
# _LC1_A9;
-- Node name is '|LEDSHOW:26|:654'
-- Equation name is '_LC1_C1', type is buried
_LC1_C1 = LCELL( _EQ081);
_EQ081 = !clk & urgen
# _LC2_A9;
-- Node name is '|LEDSHOW:26|:660'
-- Equation name is '_LC2_C1', type is buried
_LC2_C1 = LCELL( _EQ082);
_EQ082 = !clk & urgen
# _LC8_A8;
-- Node name is '|LEDSHOW:26|:666'
-- Equation name is '_LC3_C1', type is buried
_LC3_C1 = LCELL( _EQ083);
_EQ083 = !clk & urgen
# _LC7_A8;
-- Node name is '|LEDSHOW:26|:672'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = LCELL( _EQ084);
_EQ084 = !clk & urgen
# _LC4_A7;
-- Node name is '|LEDSHOW:26|:678'
-- Equation name is '_LC2_C3', type is buried
_LC2_C3 = LCELL( _EQ085);
_EQ085 = !clk & urgen
# _LC5_A7;
-- Node name is '|LEDSHOW:26|:684'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = LCELL( _EQ086);
_EQ086 = !clk & urgen
# _LC3_A10;
-- Node name is '|LEDSHOW:26|:690'
-- Equation name is '_LC1_C5', type is buried
_LC1_C5 = LCELL( _EQ087);
_EQ087 = !clk & urgen
# _LC1_B12;
-- Node name is '|LEDSHOW:26|:707'
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = LCELL( _EQ088);
_EQ088 = !clk & urgen
# _LC1_A16;
-- Node name is '|LEDSHOW:26|:713'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = LCELL( _EQ089);
_EQ089 = !clk & urgen
# _LC3_A16;
-- Node name is '|LEDSHOW:26|:719'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ090);
_EQ090 = !clk & urgen
# _LC3_A20;
-- Node name is '|LEDSHOW:26|:725'
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = LCELL( _EQ091);
_EQ091 = !clk & urgen
# _LC2_A22;
-- Node name is '|LEDSHOW:26|:731'
-- Equation name is '_LC2_C23', type is buried
_LC2_C23 = LCELL( _EQ092);
_EQ092 = !clk & urgen
# _LC4_A14;
-- Node name is '|LEDSHOW:26|:737'
-- Equation name is '_LC3_C23', type is buried
_LC3_C23 = LCELL( _EQ093);
_EQ093 = !clk & urgen
# _LC3_A14;
-- Node name is '|LEDSHOW:26|:743'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ094);
_EQ094 = !clk & urgen
# _LC5_A13;
-- Node name is '|LEDSHOW:26|:749'
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = LCELL( _EQ095);
_EQ095 = !clk & urgen
# _LC2_B18;
-- Node name is '|LEDSHOW:26|:871'
-- Equation name is '_LC2_A7', type is buried
!_LC2_A7 = _LC2_A7~NOT;
_LC2_A7~NOT = LCELL( _EQ096);
_EQ096 = _LC2_C9
# _LC2_C12;
-- Node name is '|LEDSHOW:26|:960'
-- Equation name is '_LC4_B18', type is buried
!_LC4_B18 = _LC4_B18~NOT;
_LC4_B18~NOT = LCELL( _EQ097);
_EQ097 = !_LC2_C9
# _LC2_C12;
Project Informationd:\ygcfile1\se-5m\test\file\top(sch)\traffic light\light.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,719K
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