📄 light.rpt
字号:
53 - - - 20 OUTPUT 0 1 0 0 r2
24 - - B -- OUTPUT 0 1 0 0 y1
52 - - - 19 OUTPUT 0 1 0 0 y2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:d:\ygcfile1\se-5m\test\file\top(sch)\traffic light\light.rpt
light
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 04 AND2 0 3 0 3 |LEDCONTROL:24|LPM_ADD_SUB:121|addcore:adder|:71
- 3 - C 04 AND2 0 3 0 2 |LEDCONTROL:24|LPM_ADD_SUB:121|addcore:adder|:79
- 2 - C 09 DFFE + 1 3 0 12 |LEDCONTROL:24|:4
- 2 - C 12 DFFE + 1 4 0 11 |LEDCONTROL:24|:6
- 4 - B 08 DFFE + 0 3 0 8 |LEDCONTROL:24|:9
- 2 - B 10 DFFE + 0 3 0 9 |LEDCONTROL:24|:11
- 5 - C 01 DFFE + 1 3 0 4 |LEDCONTROL:24|count6 (|LEDCONTROL:24|:13)
- 4 - C 01 DFFE + 2 2 0 5 |LEDCONTROL:24|count5 (|LEDCONTROL:24|:14)
- 4 - C 04 DFFE + 1 3 0 5 |LEDCONTROL:24|count4 (|LEDCONTROL:24|:15)
- 1 - C 04 DFFE + 2 2 0 10 |LEDCONTROL:24|count3 (|LEDCONTROL:24|:16)
- 2 - C 04 DFFE + 1 4 0 5 |LEDCONTROL:24|count2 (|LEDCONTROL:24|:17)
- 3 - C 11 DFFE + 2 3 0 8 |LEDCONTROL:24|count1 (|LEDCONTROL:24|:18)
- 1 - C 07 DFFE + 2 3 0 9 |LEDCONTROL:24|count0 (|LEDCONTROL:24|:19)
- 3 - C 05 DFFE + 1 1 0 1 |LEDCONTROL:24|subtemp (|LEDCONTROL:24|:20)
- 6 - C 01 OR2 1 3 0 1 |LEDCONTROL:24|:149
- 7 - C 04 OR2 1 3 0 1 |LEDCONTROL:24|:161
- 4 - B 02 OR2 s 0 4 0 2 |LEDCONTROL:24|~201~1
- 8 - B 06 AND2 s 0 3 0 1 |LEDCONTROL:24|~201~2
- 5 - B 02 OR2 ! 0 4 0 5 |LEDCONTROL:24|:201
- 3 - B 02 OR2 ! 0 4 0 5 |LEDCONTROL:24|:216
- 2 - B 02 AND2 s ! 0 2 0 1 |LEDCONTROL:24|~231~1
- 1 - B 02 AND2 0 4 0 7 |LEDCONTROL:24|:231
- 1 - B 03 AND2 s 0 3 0 5 |LEDCONTROL:24|~246~1
- 2 - B 01 AND2 s 0 3 0 5 |LEDCONTROL:24|~246~2
- 4 - B 10 OR2 s 0 2 0 1 |LEDCONTROL:24|~261~1
- 6 - B 10 OR2 ! 0 4 0 3 |LEDCONTROL:24|:261
- 1 - B 10 OR2 s 0 4 0 3 |LEDCONTROL:24|~330~1
- 5 - B 10 OR2 s 0 4 0 6 |LEDCONTROL:24|~360~1
- 1 - C 08 AND2 s 0 2 0 4 |LEDCONTROL:24|~386~1
- 2 - B 11 OR2 s 0 4 0 2 |LEDCONTROL:24|~404~1
- 6 - C 04 OR2 s 1 3 0 1 |LEDCONTROL:24|~422~1
- 5 - B 06 AND2 s 0 2 0 1 |LEDCONTROL:24|~440~1
- 2 - C 11 OR2 s 1 3 0 1 |LEDCONTROL:24|~440~2
- 2 - B 06 OR2 s 0 4 0 1 |LEDCONTROL:24|~440~3
- 1 - B 09 OR2 s 0 3 0 1 |LEDCONTROL:24|~456~1
- 7 - B 07 OR2 s 0 4 0 4 |LEDCONTROL:24|~468~1
- 2 - B 05 OR2 0 4 0 1 |LEDCONTROL:24|:483
- 3 - C 06 AND2 s ! 0 2 0 3 |LEDCONTROL:24|~510~1
- 3 - B 10 OR2 s 0 4 0 1 |LEDCONTROL:24|~528~1
- 2 - C 05 AND2 1 1 0 22 |LEDCONTROL:24|:557
- 7 - A 16 OR2 s 0 3 0 1 |LEDSHOW:26|LPM_ADD_SUB:190|addcore:adder|pcarry5~1
- 6 - A 16 OR2 0 4 0 2 |LEDSHOW:26|LPM_ADD_SUB:190|addcore:adder|pcarry5
- 5 - A 16 OR2 0 3 0 1 |LEDSHOW:26|LPM_ADD_SUB:190|addcore:adder|:155
- 2 - A 14 OR2 0 3 0 1 |LEDSHOW:26|LPM_ADD_SUB:231|addcore:adder|pcarry2
- 4 - A 16 OR2 0 3 0 2 |LEDSHOW:26|LPM_ADD_SUB:231|addcore:adder|pcarry5
- 1 - A 14 OR2 0 3 0 1 |LEDSHOW:26|LPM_ADD_SUB:231|addcore:adder|:150
- 2 - A 16 OR2 0 3 0 1 |LEDSHOW:26|LPM_ADD_SUB:231|addcore:adder|:155
- 3 - A 09 OR2 s 0 3 0 1 |LEDSHOW:26|LPM_ADD_SUB:470|addcore:adder|pcarry5~1
- 4 - A 09 OR2 0 4 0 2 |LEDSHOW:26|LPM_ADD_SUB:470|addcore:adder|pcarry5
- 5 - A 09 OR2 0 3 0 1 |LEDSHOW:26|LPM_ADD_SUB:470|addcore:adder|:155
- 1 - A 07 OR2 0 3 0 1 |LEDSHOW:26|LPM_ADD_SUB:511|addcore:adder|pcarry2
- 8 - A 09 OR2 0 3 0 2 |LEDSHOW:26|LPM_ADD_SUB:511|addcore:adder|pcarry5
- 3 - A 07 OR2 0 3 0 1 |LEDSHOW:26|LPM_ADD_SUB:511|addcore:adder|:150
- 7 - A 09 OR2 0 3 0 1 |LEDSHOW:26|LPM_ADD_SUB:511|addcore:adder|:155
- 3 - B 04 DFFE 1 2 1 0 |LEDSHOW:26|:8
- 7 - B 12 DFFE 1 3 1 0 |LEDSHOW:26|:10
- 5 - B 12 DFFE 1 3 1 0 |LEDSHOW:26|:12
- 2 - C 19 DFFE 1 2 1 0 |LEDSHOW:26|:14
- 1 - C 17 DFFE 1 3 1 0 |LEDSHOW:26|:16
- 1 - C 19 DFFE 1 3 1 0 |LEDSHOW:26|:18
- 1 - A 16 DFFE 0 5 0 3 |LEDSHOW:26|count27 (|LEDSHOW:26|:44)
- 3 - A 16 DFFE 0 5 0 4 |LEDSHOW:26|count26 (|LEDSHOW:26|:45)
- 3 - A 20 DFFE 0 4 0 3 |LEDSHOW:26|count25 (|LEDSHOW:26|:46)
- 2 - A 22 DFFE 0 3 0 4 |LEDSHOW:26|count24 (|LEDSHOW:26|:47)
- 4 - A 14 DFFE 0 4 0 3 |LEDSHOW:26|count23 (|LEDSHOW:26|:48)
- 3 - A 14 DFFE 0 5 0 5 |LEDSHOW:26|count22 (|LEDSHOW:26|:49)
- 5 - A 13 DFFE 0 4 0 5 |LEDSHOW:26|count21 (|LEDSHOW:26|:50)
- 2 - B 18 DFFE 0 4 0 6 |LEDSHOW:26|count20 (|LEDSHOW:26|:51)
- 1 - A 09 DFFE 0 5 0 3 |LEDSHOW:26|count17 (|LEDSHOW:26|:63)
- 2 - A 09 DFFE 0 5 0 4 |LEDSHOW:26|count16 (|LEDSHOW:26|:64)
- 8 - A 08 DFFE 0 4 0 3 |LEDSHOW:26|count15 (|LEDSHOW:26|:65)
- 7 - A 08 DFFE 0 3 0 4 |LEDSHOW:26|count14 (|LEDSHOW:26|:66)
- 4 - A 07 DFFE 0 4 0 3 |LEDSHOW:26|count13 (|LEDSHOW:26|:67)
- 5 - A 07 DFFE 0 5 0 5 |LEDSHOW:26|count12 (|LEDSHOW:26|:68)
- 3 - A 10 DFFE 0 4 0 5 |LEDSHOW:26|count11 (|LEDSHOW:26|:69)
- 1 - B 12 DFFE 0 4 0 6 |LEDSHOW:26|count10 (|LEDSHOW:26|:70)
- 1 - A 15 OR2 ! 0 4 0 8 |LEDSHOW:26|:129
- 8 - A 16 OR2 0 4 0 1 |LEDSHOW:26|:269
- 2 - A 12 OR2 ! 0 4 0 8 |LEDSHOW:26|:409
- 6 - A 09 OR2 0 4 0 1 |LEDSHOW:26|:549
- 1 - A 03 OR2 2 1 1 0 |LEDSHOW:26|:648
- 1 - C 01 OR2 2 1 1 0 |LEDSHOW:26|:654
- 2 - C 01 OR2 2 1 1 0 |LEDSHOW:26|:660
- 3 - C 01 OR2 2 1 1 0 |LEDSHOW:26|:666
- 1 - C 03 OR2 2 1 1 0 |LEDSHOW:26|:672
- 2 - C 03 OR2 2 1 1 0 |LEDSHOW:26|:678
- 3 - C 03 OR2 2 1 1 0 |LEDSHOW:26|:684
- 1 - C 05 OR2 2 1 1 0 |LEDSHOW:26|:690
- 1 - C 11 OR2 2 1 1 0 |LEDSHOW:26|:707
- 1 - C 13 OR2 2 1 1 0 |LEDSHOW:26|:713
- 1 - C 21 OR2 2 1 1 0 |LEDSHOW:26|:719
- 1 - C 23 OR2 2 1 1 0 |LEDSHOW:26|:725
- 2 - C 23 OR2 2 1 1 0 |LEDSHOW:26|:731
- 3 - C 23 OR2 2 1 1 0 |LEDSHOW:26|:737
- 1 - A 24 OR2 2 1 1 0 |LEDSHOW:26|:743
- 2 - A 24 OR2 2 1 1 0 |LEDSHOW:26|:749
- 2 - A 07 OR2 ! 0 2 0 1 |LEDSHOW:26|:871
- 4 - B 18 OR2 ! 0 2 0 1 |LEDSHOW:26|:960
- 2 - C 02 SOFT s ! 1 0 0 3 reset~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:d:\ygcfile1\se-5m\test\file\top(sch)\traffic light\light.rpt
light
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 10/ 48( 20%) 10/ 48( 20%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 5/ 96( 5%) 20/ 48( 41%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 6/ 96( 6%) 24/ 48( 50%) 5/ 48( 10%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\ygcfile1\se-5m\test\file\top(sch)\traffic light\light.rpt
light
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 29 clk
LCELL 22 |LEDCONTROL:24|:557
Device-Specific Information:d:\ygcfile1\se-5m\test\file\top(sch)\traffic light\light.rpt
light
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 10 reset
Device-Specific Information:d:\ygcfile1\se-5m\test\file\top(sch)\traffic light\light.rpt
light
** EQUATIONS **
clk : INPUT;
reset : INPUT;
urgen : INPUT;
-- Node name is 'g1'
-- Equation name is 'g1', type is output
g1 = _LC7_B12;
-- Node name is 'g2'
-- Equation name is 'g2', type is output
g2 = _LC1_C17;
-- Node name is 'led10'
-- Equation name is 'led10', type is output
led10 = _LC1_C5;
-- Node name is 'led11'
-- Equation name is 'led11', type is output
led11 = _LC3_C3;
-- Node name is 'led12'
-- Equation name is 'led12', type is output
led12 = _LC2_C3;
-- Node name is 'led13'
-- Equation name is 'led13', type is output
led13 = _LC1_C3;
-- Node name is 'led14'
-- Equation name is 'led14', type is output
led14 = _LC3_C1;
-- Node name is 'led15'
-- Equation name is 'led15', type is output
led15 = _LC2_C1;
-- Node name is 'led16'
-- Equation name is 'led16', type is output
led16 = _LC1_C1;
-- Node name is 'led17'
-- Equation name is 'led17', type is output
led17 = _LC1_A3;
-- Node name is 'led20'
-- Equation name is 'led20', type is output
led20 = _LC2_A24;
-- Node name is 'led21'
-- Equation name is 'led21', type is output
led21 = _LC1_A24;
-- Node name is 'led22'
-- Equation name is 'led22', type is output
led22 = _LC3_C23;
-- Node name is 'led23'
-- Equation name is 'led23', type is output
led23 = _LC2_C23;
-- Node name is 'led24'
-- Equation name is 'led24', type is output
led24 = _LC1_C23;
-- Node name is 'led25'
-- Equation name is 'led25', type is output
led25 = _LC1_C21;
-- Node name is 'led26'
-- Equation name is 'led26', type is output
led26 = _LC1_C13;
-- Node name is 'led27'
-- Equation name is 'led27', type is output
led27 = _LC1_C11;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC2_C2, type is buried.
-- synthesized logic cell
!_LC2_C2 = _LC2_C2~NOT;
_LC2_C2~NOT = LCELL(!reset);
-- Node name is 'r1'
-- Equation name is 'r1', type is output
r1 = _LC3_B4;
-- Node name is 'r2'
-- Equation name is 'r2', type is output
r2 = _LC2_C19;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC5_B12;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC1_C19;
-- Node name is '|LEDCONTROL:24|:19' = '|LEDCONTROL:24|count0'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = DFFE( _EQ001, GLOBAL( clk), !reset, VCC, VCC);
_EQ001 = _LC8_B6 & !urgen
# !_LC1_C8 & !urgen
# _LC1_B9 & _LC1_C8 & urgen;
-- Node name is '|LEDCONTROL:24|:18' = '|LEDCONTROL:24|count1'
-- Equation name is '_LC3_C11', type is buried
_LC3_C11 = DFFE( _EQ002, GLOBAL( clk), !reset, VCC, VCC);
_EQ002 = _LC1_C8 & _LC2_C11
# _LC1_C8 & _LC2_B6 & !urgen;
-- Node name is '|LEDCONTROL:24|:17' = '|LEDCONTROL:24|count2'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = DFFE( _EQ003, GLOBAL( clk), !reset, VCC, VCC);
_EQ003 = _LC1_B2 & _LC1_C8 & _LC6_C4
# _LC1_B10 & _LC1_C8 & _LC6_C4;
-- Node name is '|LEDCONTROL:24|:16' = '|LEDCONTROL:24|count3'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = DFFE( _EQ004, GLOBAL( clk), !reset, VCC, VCC);
_EQ004 = _LC1_C4 & _LC2_B11 & urgen
# _LC1_C4 & _LC2_B11 & !_LC5_C4
# !_LC1_C4 & _LC2_B11 & _LC5_C4 & !urgen;
-- Node name is '|LEDCONTROL:24|:15' = '|LEDCONTROL:24|count4'
-- Equation name is '_LC4_C4', type is buried
_LC4_C4 = DFFE( _EQ005, GLOBAL( clk), !reset, VCC, VCC);
_EQ005 = _LC1_B10 & !_LC3_C6 & _LC7_C4;
-- Node name is '|LEDCONTROL:24|:14' = '|LEDCONTROL:24|count5'
-- Equation name is '_LC4_C1', type is buried
_LC4_C1 = DFFE( _EQ006, GLOBAL( clk), !reset, VCC, VCC);
_EQ006 = _LC2_B11 & _LC4_C1 & urgen
# _LC2_B11 & !_LC3_C4 & _LC4_C1
# _LC2_B11 & _LC3_C4 & !_LC4_C1 & !urgen;
-- Node name is '|LEDCONTROL:24|:13' = '|LEDCONTROL:24|count6'
-- Equation name is '_LC5_C1', type is buried
_LC5_C1 = DFFE( _EQ007, GLOBAL( clk), !reset, VCC, VCC);
_EQ007 = _LC1_B10 & !_LC3_C6 & _LC6_C1;
-- Node name is '|LEDCONTROL:24|LPM_ADD_SUB:121|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C4', type is buried
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