📄 floor.rpt
字号:
- 1 - C 15 OR2 s ! 0 3 0 4 |FCONTROL:44|~1376~1
- 1 - C 19 OR2 ! 0 2 0 6 |FCONTROL:44|:1376
- 1 - C 13 OR2 s ! 0 4 0 6 |FCONTROL:44|~1390~1
- 5 - B 01 OR2 s 0 4 0 1 |FCONTROL:44|~1390~2
- 2 - C 09 OR2 ! 0 2 0 6 |FCONTROL:44|:1390
- 5 - C 11 OR2 ! 0 3 0 7 |FCONTROL:44|:1404
- 4 - C 16 OR2 s 0 4 0 1 |FCONTROL:44|~1717~1
- 5 - C 24 OR2 s 0 4 0 1 |FCONTROL:44|~1729~1
- 4 - C 03 OR2 s 0 4 0 1 |FCONTROL:44|~1741~1
- 5 - C 03 AND2 s 0 2 0 1 |FCONTROL:44|~1741~2
- 6 - C 03 OR2 s 0 4 0 1 |FCONTROL:44|~1747~1
- 7 - B 08 OR2 0 2 0 3 |FCONTROL:44|:2060
- 8 - B 08 OR2 0 2 0 2 |FCONTROL:44|:2094
- 3 - B 08 OR2 0 2 0 1 |FCONTROL:44|:2128
- 7 - B 11 OR2 s 0 4 0 1 |FCONTROL:44|~2178~1
- 6 - B 11 OR2 ! 0 3 0 1 |FCONTROL:44|:2186
- 5 - B 11 OR2 s 0 4 0 1 |FCONTROL:44|~2189~1
- 4 - B 11 OR2 s 0 4 0 1 |FCONTROL:44|~2200~1
- 3 - B 11 OR2 s 0 4 0 1 |FCONTROL:44|~2200~2
- 6 - B 08 OR2 s ! 0 4 0 1 |FCONTROL:44|~2225~1
- 5 - B 08 OR2 s 0 4 0 1 |FCONTROL:44|~2225~2
- 4 - B 08 OR2 s 0 4 0 1 |FCONTROL:44|~2225~3
- 2 - B 11 OR2 0 4 0 2 |FCONTROL:44|:2227
- 4 - B 01 OR2 s 0 3 0 1 |FCONTROL:44|~2312~1
- 3 - B 01 OR2 s ! 0 4 0 1 |FCONTROL:44|~2312~2
- 2 - B 01 OR2 s 0 4 0 1 |FCONTROL:44|~2312~3
- 6 - B 01 OR2 ! 0 4 0 4 |FCONTROL:44|:2312
- 1 - B 08 OR2 s ! 0 4 0 2 |FCONTROL:44|~2409~1
- 2 - B 08 OR2 s ! 0 4 0 2 |FCONTROL:44|~2409~2
- 2 - B 17 OR2 s ! 0 4 0 2 |FCONTROL:44|~2409~3
- 4 - B 13 OR2 ! 0 2 0 7 |FCONTROL:44|:2480
- 3 - A 23 OR2 0 2 0 4 |FCONTROL:44|:2495
- 8 - B 13 AND2 0 3 0 3 |FCONTROL:44|:2502
- 6 - B 13 OR2 0 4 0 3 |FCONTROL:44|:2567
- 4 - B 17 OR2 s ! 0 4 0 3 |FCONTROL:44|~2569~1
- 5 - B 13 AND2 0 2 0 1 |FCONTROL:44|:2584
- 3 - C 05 AND2 ! 0 3 0 4 |FCONTROL:44|:2609
- 2 - B 02 AND2 s 0 2 0 1 |FCONTROL:44|~2626~1
- 1 - B 09 OR2 ! 0 4 0 6 |FCONTROL:44|:2626
- 3 - B 02 OR2 0 4 0 4 |FCONTROL:44|:2647
- 1 - B 02 OR2 0 2 0 2 |FCONTROL:44|:2651
- 5 - B 02 OR2 ! 0 4 0 4 |FCONTROL:44|:2668
- 3 - B 18 OR2 0 2 0 3 |FCONTROL:44|:2711
- 7 - B 17 OR2 0 4 0 3 |FCONTROL:44|:2739
- 5 - B 17 OR2 0 3 0 1 |FCONTROL:44|:2785
- 1 - A 19 OR2 0 4 1 0 |FCONTROL:44|:2817
- 8 - B 05 DFFE 0 2 1 2 |KEY:45|:23
- 6 - B 07 DFFE 0 2 1 4 |KEY:45|:25
- 3 - B 10 DFFE 0 2 1 5 |KEY:45|:27
- 2 - B 06 DFFE 0 2 1 2 |KEY:45|:29
- 1 - B 03 DFFE 0 2 1 2 |KEY:45|:31
- 7 - A 07 DFFE 0 2 1 2 |KEY:45|:33
- 5 - A 06 DFFE 0 2 1 4 |KEY:45|:35
- 3 - A 08 DFFE 0 2 1 4 |KEY:45|:37
- 1 - A 05 DFFE 0 2 1 5 |KEY:45|:39
- 1 - C 01 DFFE 0 2 1 7 |KEY:45|:41
- 3 - C 12 DFFE + 1 0 0 1 |KEY:45|up1 (|KEY:45|:43)
- 2 - C 12 DFFE + 1 0 0 1 |KEY:45|up2 (|KEY:45|:44)
- 6 - C 12 DFFE + 1 0 0 1 |KEY:45|up3 (|KEY:45|:45)
- 1 - B 06 DFFE + 1 0 0 1 |KEY:45|dn2 (|KEY:45|:46)
- 2 - B 03 DFFE + 1 0 0 1 |KEY:45|dn3 (|KEY:45|:47)
- 1 - A 07 DFFE + 1 0 0 1 |KEY:45|dn4 (|KEY:45|:48)
- 1 - A 06 DFFE + 1 0 0 1 |KEY:45|to1 (|KEY:45|:49)
- 2 - A 08 DFFE + 1 0 0 1 |KEY:45|to2 (|KEY:45|:50)
- 3 - A 05 DFFE + 1 0 0 1 |KEY:45|to3 (|KEY:45|:51)
- 5 - C 01 DFFE + 1 0 0 1 |KEY:45|to4 (|KEY:45|:52)
- 4 - C 04 AND2 ! 1 1 0 1 |KEY:45|:100
- 7 - C 04 AND2 ! 1 1 0 1 |KEY:45|:110
- 2 - B 19 AND2 ! 1 1 0 1 |KEY:45|:120
- 2 - C 04 AND2 ! 1 1 0 1 |KEY:45|:130
- 2 - C 02 AND2 ! 1 1 0 1 |KEY:45|:140
- 2 - A 07 AND2 ! 1 1 0 1 |KEY:45|:150
- 2 - A 06 AND2 ! 1 1 0 1 |KEY:45|:160
- 1 - A 08 AND2 ! 1 1 0 1 |KEY:45|:170
- 2 - A 05 AND2 ! 1 1 0 1 |KEY:45|:180
- 2 - C 01 AND2 ! 1 1 0 1 |KEY:45|:190
- 3 - A 01 SOFT s ! 1 0 0 16 reset~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\a\floor\floor.rpt
floor
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 13/ 96( 13%) 12/ 48( 25%) 24/ 48( 50%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 18/ 96( 18%) 20/ 48( 41%) 8/ 48( 16%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 20/ 96( 20%) 5/ 48( 10%) 8/ 48( 16%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\a\floor\floor.rpt
floor
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 37 clk16
INPUT 10 clk1024
DFF 1 |KEY:45|to3
DFF 1 |KEY:45|to2
DFF 1 |KEY:45|to1
DFF 1 |KEY:45|dn4
DFF 1 |KEY:45|dn3
DFF 1 |KEY:45|dn2
DFF 1 |KEY:45|up3
DFF 1 |KEY:45|up2
DFF 1 |KEY:45|up1
DFF 1 |KEY:45|to4
Device-Specific Information: c:\a\floor\floor.rpt
floor
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 32 reset
LCELL 1 |KEY:45|:190
LCELL 1 |KEY:45|:180
LCELL 1 |KEY:45|:170
LCELL 1 |KEY:45|:160
LCELL 1 |KEY:45|:150
LCELL 1 |KEY:45|:140
LCELL 1 |KEY:45|:130
LCELL 1 |KEY:45|:120
LCELL 1 |KEY:45|:110
LCELL 1 |KEY:45|:100
Device-Specific Information: c:\a\floor\floor.rpt
floor
** EQUATIONS **
clk16 : INPUT;
clk1024 : INPUT;
dn2 : INPUT;
dn3 : INPUT;
dn4 : INPUT;
reset : INPUT;
to1 : INPUT;
to2 : INPUT;
to3 : INPUT;
to4 : INPUT;
up1 : INPUT;
up2 : INPUT;
up3 : INPUT;
-- Node name is 'dnled'
-- Equation name is 'dnled', type is output
dnled = !_LC1_B19;
-- Node name is 'floor0'
-- Equation name is 'floor0', type is output
floor0 = _LC3_A14;
-- Node name is 'floor1'
-- Equation name is 'floor1', type is output
floor1 = _LC1_A21;
-- Node name is 'floor2'
-- Equation name is 'floor2', type is output
floor2 = _LC2_A23;
-- Node name is 'floor3'
-- Equation name is 'floor3', type is output
floor3 = _LC1_A23;
-- Node name is 'ldn2'
-- Equation name is 'ldn2', type is output
ldn2 = _LC2_B6;
-- Node name is 'ldn3'
-- Equation name is 'ldn3', type is output
ldn3 = _LC1_B3;
-- Node name is 'ldn4'
-- Equation name is 'ldn4', type is output
ldn4 = _LC7_A7;
-- Node name is 'lto1'
-- Equation name is 'lto1', type is output
lto1 = _LC5_A6;
-- Node name is 'lto2'
-- Equation name is 'lto2', type is output
lto2 = _LC3_A8;
-- Node name is 'lto3'
-- Equation name is 'lto3', type is output
lto3 = _LC1_A5;
-- Node name is 'lto4'
-- Equation name is 'lto4', type is output
lto4 = _LC1_C1;
-- Node name is 'lup1'
-- Equation name is 'lup1', type is output
lup1 = _LC8_B5;
-- Node name is 'lup2'
-- Equation name is 'lup2', type is output
lup2 = _LC6_B7;
-- Node name is 'lup3'
-- Equation name is 'lup3', type is output
lup3 = _LC3_B10;
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