📄 floor.rpt
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B17 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 12/22( 54%)
B18 5/ 8( 62%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
B19 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 5/22( 22%)
C1 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 12/22( 54%)
C2 5/ 8( 62%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 7/22( 31%)
C3 6/ 8( 75%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 9/22( 40%)
C4 7/ 8( 87%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 7/22( 31%)
C5 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C12 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
C13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C16 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
C19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 3/22( 13%)
C21 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 5/22( 22%)
C22 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 5/22( 22%)
C24 5/ 8( 62%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 28/53 ( 52%)
Total logic cells used: 181/576 ( 31%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.07/4 ( 76%)
Total fan-in: 556/2304 ( 24%)
Total input pins required: 13
Total input I/O cell registers required: 0
Total output pins required: 17
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 181
Total flipflops required: 57
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 53/ 576 ( 9%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 3 1 0 0 3 3 3 3 7 1 0 0 0 4 1 1 0 1 1 5 8 1 1 6 8 61/0
B: 6 4 2 0 1 2 1 8 1 1 8 0 0 8 0 1 1 8 5 2 0 0 0 0 0 59/0
C: 7 5 6 7 1 1 1 1 1 0 1 3 0 1 0 1 4 0 0 1 1 6 8 0 5 61/0
Total: 16 10 8 7 5 6 5 12 9 2 9 3 0 13 1 3 5 9 6 8 9 7 9 6 13 181/0
Device-Specific Information: c:\a\floor\floor.rpt
floor
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
43 - - - -- INPUT G 0 0 0 0 clk16
1 - - - -- INPUT G 0 0 0 0 clk1024
35 - - - 06 INPUT 0 0 0 1 dn2
36 - - - 07 INPUT 0 0 0 1 dn3
37 - - - 09 INPUT 0 0 0 1 dn4
49 - - - 16 INPUT 0 0 0 32 reset
38 - - - 10 INPUT 0 0 0 1 to1
39 - - - 11 INPUT 0 0 0 1 to2
47 - - - 14 INPUT 0 0 0 1 to3
48 - - - 15 INPUT 0 0 0 1 to4
28 - - C -- INPUT 0 0 0 1 up1
29 - - C -- INPUT 0 0 0 1 up2
30 - - C -- INPUT 0 0 0 1 up3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\a\floor\floor.rpt
floor
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
52 - - - 19 OUTPUT 0 1 0 0 dnled
72 - - A -- OUTPUT 0 1 0 0 floor0
73 - - A -- OUTPUT 0 1 0 0 floor1
78 - - - 24 OUTPUT 0 1 0 0 floor2
79 - - - 24 OUTPUT 0 1 0 0 floor3
22 - - B -- OUTPUT 0 1 0 0 ldn2
21 - - B -- OUTPUT 0 1 0 0 ldn3
19 - - A -- OUTPUT 0 1 0 0 ldn4
18 - - A -- OUTPUT 0 1 0 0 lto1
17 - - A -- OUTPUT 0 1 0 0 lto2
16 - - A -- OUTPUT 0 1 0 0 lto3
11 - - - 01 OUTPUT 0 1 0 0 lto4
25 - - B -- OUTPUT 0 1 0 0 lup1
24 - - B -- OUTPUT 0 1 0 0 lup2
23 - - B -- OUTPUT 0 1 0 0 lup3
53 - - - 20 OUTPUT 0 1 0 0 openled
51 - - - 18 OUTPUT 0 1 0 0 upled
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\a\floor\floor.rpt
floor
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 21 AND2 0 3 0 4 |FCONTROL:44|LPM_ADD_SUB:458|addcore:adder|:125
- 6 - C 22 AND2 0 2 0 1 |FCONTROL:44|LPM_ADD_SUB:458|addcore:adder|:129
- 5 - C 22 AND2 0 4 0 2 |FCONTROL:44|LPM_ADD_SUB:458|addcore:adder|:137
- 2 - B 13 OR2 0 3 0 2 |FCONTROL:44|LPM_ADD_SUB:600|addcore:adder|pcarry0
- 3 - B 13 OR2 0 4 0 2 |FCONTROL:44|LPM_ADD_SUB:600|addcore:adder|pcarry1
- 7 - B 13 OR2 0 4 0 1 |FCONTROL:44|LPM_ADD_SUB:600|addcore:adder|:70
- 2 - A 15 OR2 s 0 2 0 1 |FCONTROL:44|LPM_ADD_SUB:600|addcore:adder|~71~1
- 3 - A 19 OR2 0 4 0 1 |FCONTROL:44|LPM_ADD_SUB:600|addcore:adder|:72
- 2 - B 18 OR2 0 4 0 2 |FCONTROL:44|LPM_ADD_SUB:631|addcore:adder|pcarry0
- 4 - B 18 OR2 0 4 0 2 |FCONTROL:44|LPM_ADD_SUB:631|addcore:adder|pcarry1
- 1 - B 15 OR2 0 4 0 1 |FCONTROL:44|LPM_ADD_SUB:631|addcore:adder|:65
- 2 - A 24 AND2 ! 0 3 0 4 |FCONTROL:44|LPM_ADD_SUB:654|addcore:adder|pcarry2
- 2 - A 09 AND2 0 4 0 5 |FCONTROL:44|LPM_ADD_SUB:769|addcore:adder|:71
- 2 - A 01 OR2 0 2 0 1 |FCONTROL:44|LPM_ADD_SUB:769|addcore:adder|:83
- 4 - A 09 OR2 0 3 0 1 |FCONTROL:44|LPM_ADD_SUB:769|addcore:adder|:84
- 1 - A 09 OR2 0 4 0 1 |FCONTROL:44|LPM_ADD_SUB:769|addcore:adder|:85
- 2 - A 13 OR2 0 2 0 1 |FCONTROL:44|LPM_ADD_SUB:769|addcore:adder|:86
- 3 - A 13 OR2 0 3 0 1 |FCONTROL:44|LPM_ADD_SUB:769|addcore:adder|:87
- 6 - A 23 AND2 0 3 0 1 |FCONTROL:44|LPM_ADD_SUB:948|addcore:adder|:59
- 1 - A 10 AND2 ! 0 2 0 6 |FCONTROL:44|LPM_ADD_SUB:969|addcore:adder|pcarry1
- 1 - A 23 DFFE + 1 3 1 14 |FCONTROL:44|:16
- 2 - A 23 DFFE + 1 3 1 23 |FCONTROL:44|:18
- 1 - A 21 DFFE + 1 3 1 20 |FCONTROL:44|:20
- 3 - A 14 DFFE + ! 1 2 1 21 |FCONTROL:44|:22
- 1 - C 04 DFFE + 0 3 0 1 |FCONTROL:44|:24
- 6 - C 04 DFFE + 0 3 0 1 |FCONTROL:44|:26
- 1 - C 24 DFFE + 0 3 0 1 |FCONTROL:44|:28
- 5 - C 04 DFFE + 0 3 0 1 |FCONTROL:44|:30
- 5 - C 02 DFFE + 0 3 0 1 |FCONTROL:44|:32
- 1 - C 02 DFFE + 0 3 0 1 |FCONTROL:44|:34
- 2 - C 03 DFFE + 0 3 0 1 |FCONTROL:44|:36
- 1 - C 03 DFFE + 0 3 0 1 |FCONTROL:44|:38
- 2 - C 24 DFFE + 0 3 0 1 |FCONTROL:44|:40
- 1 - C 16 DFFE + 0 3 0 1 |FCONTROL:44|:42
- 3 - A 20 DFFE + 1 3 0 10 |FCONTROL:44|statesport1 (|FCONTROL:44|:44)
- 2 - A 20 DFFE + 1 3 0 1 |FCONTROL:44|statesport0 (|FCONTROL:44|:45)
- 1 - C 22 DFFE + 1 3 0 1 |FCONTROL:44|countopen7 (|FCONTROL:44|:46)
- 8 - C 22 DFFE + 1 2 0 3 |FCONTROL:44|countopen6 (|FCONTROL:44|:47)
- 4 - C 22 DFFE + 1 3 0 2 |FCONTROL:44|countopen5 (|FCONTROL:44|:48)
- 7 - C 22 DFFE + 1 3 0 4 |FCONTROL:44|countopen4 (|FCONTROL:44|:49)
- 1 - C 20 DFFE + 1 2 0 4 |FCONTROL:44|countopen3 (|FCONTROL:44|:50)
- 6 - C 21 DFFE + 1 3 0 2 |FCONTROL:44|countopen2 (|FCONTROL:44|:51)
- 5 - C 21 DFFE + 1 2 0 3 |FCONTROL:44|countopen1 (|FCONTROL:44|:52)
- 4 - C 21 DFFE + 1 1 0 4 |FCONTROL:44|countopen0 (|FCONTROL:44|:53)
- 1 - B 19 DFFE +s ! 1 3 1 0 |FCONTROL:44|state~1 (|FCONTROL:44|~54~1)
- 3 - B 17 DFFE + ! 1 3 1 21 |FCONTROL:44|state (|FCONTROL:44|:54)
- 2 - A 19 DFFE + 1 4 0 4 |FCONTROL:44|directfloor3 (|FCONTROL:44|:55)
- 1 - A 24 DFFE + 1 4 0 2 |FCONTROL:44|directfloor2 (|FCONTROL:44|:56)
- 3 - A 24 DFFE + 1 4 0 3 |FCONTROL:44|directfloor1 (|FCONTROL:44|:57)
- 4 - A 24 DFFE + 1 4 0 4 |FCONTROL:44|directfloor0 (|FCONTROL:44|:58)
- 1 - A 20 DFFE + 1 3 0 3 |FCONTROL:44|directclose (|FCONTROL:44|:59)
- 1 - A 13 DFFE + 0 4 0 5 |FCONTROL:44|countsport5 (|FCONTROL:44|:68)
- 7 - A 13 DFFE + 0 4 0 8 |FCONTROL:44|countsport4 (|FCONTROL:44|:69)
- 6 - A 09 DFFE + 0 4 0 3 |FCONTROL:44|countsport3 (|FCONTROL:44|:70)
- 5 - A 09 DFFE + 0 4 0 4 |FCONTROL:44|countsport2 (|FCONTROL:44|:71)
- 1 - A 01 DFFE + 0 4 0 5 |FCONTROL:44|countsport1 (|FCONTROL:44|:72)
- 6 - A 02 DFFE + 0 3 0 5 |FCONTROL:44|countsport0 (|FCONTROL:44|:73)
- 1 - B 13 OR2 ! 0 2 0 8 |FCONTROL:44|:549
- 1 - B 18 OR2 ! 0 2 0 7 |FCONTROL:44|:559
- 6 - A 20 AND2 0 4 0 4 |FCONTROL:44|:579
- 4 - A 19 OR2 0 4 0 1 |FCONTROL:44|:679
- 5 - A 19 OR2 0 4 0 1 |FCONTROL:44|:680
- 5 - A 24 OR2 0 4 0 1 |FCONTROL:44|:690
- 6 - A 24 OR2 0 4 0 1 |FCONTROL:44|:693
- 5 - B 18 OR2 0 4 0 1 |FCONTROL:44|:706
- 7 - A 24 OR2 0 4 0 1 |FCONTROL:44|:707
- 8 - A 24 OR2 0 4 0 1 |FCONTROL:44|:717
- 5 - A 22 OR2 0 4 0 6 |FCONTROL:44|:750
- 1 - C 08 AND2 s 0 2 0 2 |FCONTROL:44|~844~1
- 3 - C 16 AND2 s 0 4 0 1 |FCONTROL:44|~844~2
- 2 - C 16 AND2 s 0 4 0 1 |FCONTROL:44|~844~3
- 3 - C 24 AND2 s 0 4 0 1 |FCONTROL:44|~844~4
- 3 - C 03 AND2 s 0 2 0 2 |FCONTROL:44|~844~5
- 4 - C 02 AND2 s 0 4 0 1 |FCONTROL:44|~844~6
- 3 - C 02 AND2 s 0 3 0 1 |FCONTROL:44|~844~7
- 3 - C 04 AND2 s 0 2 0 1 |FCONTROL:44|~844~8
- 7 - C 01 AND2 s 0 4 0 3 |FCONTROL:44|~844~9
- 4 - C 01 AND2 s 0 2 0 1 |FCONTROL:44|~844~10
- 4 - C 24 AND2 s 0 4 0 1 |FCONTROL:44|~844~11
- 3 - C 01 AND2 s 0 4 0 1 |FCONTROL:44|~844~12
- 6 - C 01 AND2 s 0 4 0 1 |FCONTROL:44|~844~13
- 3 - C 22 AND2 0 3 0 12 |FCONTROL:44|:844
- 2 - C 21 AND2 s 0 3 0 1 |FCONTROL:44|~861~1
- 3 - C 21 AND2 s 0 4 0 2 |FCONTROL:44|~861~2
- 2 - C 22 OR2 ! 0 3 0 2 |FCONTROL:44|:861
- 1 - A 17 AND2 0 4 0 4 |FCONTROL:44|:919
- 3 - A 18 AND2 0 4 0 4 |FCONTROL:44|:935
- 5 - A 23 OR2 0 4 0 1 |FCONTROL:44|:987
- 4 - A 23 OR2 0 3 0 1 |FCONTROL:44|:999
- 5 - A 20 AND2 s ! 0 3 0 1 |FCONTROL:44|~1040~1
- 7 - A 20 OR2 0 4 0 4 |FCONTROL:44|:1052
- 7 - A 09 AND2 s ! 0 3 0 1 |FCONTROL:44|~1096~1
- 3 - A 09 AND2 s ! 0 3 0 3 |FCONTROL:44|~1096~2
- 8 - A 20 OR2 s 0 4 0 1 |FCONTROL:44|~1096~3
- 4 - A 20 OR2 s 0 4 0 6 |FCONTROL:44|~1130~1
- 1 - B 01 OR2 s 0 4 0 1 |FCONTROL:44|~1239~1
- 6 - B 17 OR2 s ! 0 4 0 1 |FCONTROL:44|~1239~2
- 8 - B 11 AND2 s ! 0 4 0 1 |FCONTROL:44|~1239~3
- 1 - B 11 OR2 s ! 0 3 0 1 |FCONTROL:44|~1239~4
- 8 - B 17 OR2 s ! 0 4 0 1 |FCONTROL:44|~1239~5
- 1 - B 17 OR2 s ! 0 4 0 2 |FCONTROL:44|~1239~6
- 3 - B 16 OR2 s 0 4 0 2 |FCONTROL:44|~1239~7
- 1 - C 06 OR2 ! 0 3 0 6 |FCONTROL:44|:1348
- 1 - C 07 AND2 0 4 0 5 |FCONTROL:44|:1362
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