📄 spendgdf.rpt
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- 8 - B 06 AND2 0 3 0 2 |COUNT99:41|LPM_ADD_SUB:461|addcore:adder|:151
- 7 - C 02 AND2 0 3 0 1 |COUNT99:41|LPM_ADD_SUB:588|addcore:adder|:151
- 6 - C 02 DFFE 1 5 0 3 |COUNT99:41|mm15 (|COUNT99:41|:54)
- 3 - C 02 DFFE 1 5 0 6 |COUNT99:41|mm14 (|COUNT99:41|:55)
- 4 - C 02 DFFE 1 4 0 4 |COUNT99:41|mm13 (|COUNT99:41|:56)
- 5 - C 02 DFFE 1 5 0 4 |COUNT99:41|mm12 (|COUNT99:41|:57)
- 1 - C 06 DFFE 1 4 0 5 |COUNT99:41|mm11 (|COUNT99:41|:58)
- 5 - C 01 DFFE ! 1 4 0 4 |COUNT99:41|mm10 (|COUNT99:41|:59)
- 2 - C 09 DFFE ! 1 4 0 5 |COUNT99:41|mm9 (|COUNT99:41|:60)
- 3 - C 12 DFFE ! 1 5 0 4 |COUNT99:41|mm8 (|COUNT99:41|:61)
- 4 - C 12 DFFE 1 5 0 4 |COUNT99:41|mm7 (|COUNT99:41|:62)
- 5 - C 12 DFFE 1 4 0 4 |COUNT99:41|mm6 (|COUNT99:41|:63)
- 2 - C 12 DFFE 1 5 0 5 |COUNT99:41|mm5 (|COUNT99:41|:64)
- 1 - C 04 DFFE 1 5 0 4 |COUNT99:41|mm4 (|COUNT99:41|:65)
- 3 - C 04 DFFE 1 4 0 4 |COUNT99:41|mm3 (|COUNT99:41|:66)
- 5 - C 04 DFFE 1 4 0 4 |COUNT99:41|mm2 (|COUNT99:41|:67)
- 1 - C 05 DFFE 1 4 0 5 |COUNT99:41|mm1 (|COUNT99:41|:68)
- 2 - C 05 DFFE 1 3 0 3 |COUNT99:41|mm0 (|COUNT99:41|:69)
- 7 - B 06 OR2 0 4 0 1 |COUNT99:41|:217
- 4 - B 06 OR2 0 3 0 2 |COUNT99:41|:223
- 6 - B 08 OR2 0 4 0 2 |COUNT99:41|:229
- 5 - B 08 OR2 0 4 0 3 |COUNT99:41|:235
- 4 - B 12 OR2 0 3 0 4 |COUNT99:41|:241
- 5 - B 11 OR2 0 4 0 2 |COUNT99:41|:247
- 4 - B 11 OR2 0 3 0 3 |COUNT99:41|:253
- 7 - A 11 OR2 0 4 0 2 |COUNT99:41|:259
- 5 - A 11 OR2 0 3 0 4 |COUNT99:41|:265
- 8 - A 08 OR2 0 4 0 2 |COUNT99:41|:271
- 5 - A 08 OR2 0 3 0 4 |COUNT99:41|:277
- 4 - A 08 OR2 0 4 0 5 |COUNT99:41|:283
- 7 - C 04 OR2 ! 0 4 0 3 |COUNT99:41|:295
- 6 - C 04 OR2 ! 0 3 0 3 |COUNT99:41|:301
- 2 - C 04 OR2 ! 0 4 0 18 |COUNT99:41|:317
- 3 - B 06 OR2 0 4 0 1 |COUNT99:41|:344
- 2 - B 06 OR2 0 3 0 2 |COUNT99:41|:350
- 3 - B 08 OR2 0 4 0 2 |COUNT99:41|:356
- 1 - B 08 OR2 0 4 0 3 |COUNT99:41|:362
- 3 - B 07 OR2 0 3 0 2 |COUNT99:41|:368
- 2 - B 11 OR2 0 4 0 3 |COUNT99:41|:374
- 1 - B 11 OR2 0 3 0 3 |COUNT99:41|:380
- 4 - A 11 OR2 0 4 0 4 |COUNT99:41|:386
- 6 - A 08 OR2 ! 0 4 0 3 |COUNT99:41|:398
- 6 - C 12 OR2 ! 0 3 0 3 |COUNT99:41|:404
- 1 - C 12 OR2 ! 0 4 0 12 |COUNT99:41|:444
- 5 - B 06 OR2 0 4 0 1 |COUNT99:41|:471
- 1 - B 06 OR2 0 3 0 2 |COUNT99:41|:477
- 2 - B 01 OR2 0 4 0 3 |COUNT99:41|:483
- 6 - B 09 OR2 0 3 0 4 |COUNT99:41|:489
- 1 - B 07 OR2 ! 0 4 0 4 |COUNT99:41|:495
- 1 - B 05 OR2 ! 0 4 0 5 |COUNT99:41|:501
- 1 - B 03 OR2 ! 0 3 0 5 |COUNT99:41|:507
- 2 - C 02 OR2 ! 0 3 0 5 |COUNT99:41|:571
- 1 - C 02 OR2 0 3 0 4 |COUNT99:41|:799
- 5 - B 16 AND2 ! 0 2 0 2 |COUNT99:41|:885
- 2 - B 18 AND2 s ! 0 4 0 1 |COUNT99:41|~886~1
- 1 - B 16 AND2 0 4 0 18 |COUNT99:41|:886
- 1 - C 01 SOFT s ! 1 0 0 1 k2~1
- 1 - A 11 DFFE + 0 4 1 0 |SAO:42|:34
- 1 - A 13 DFFE + 0 3 1 0 |SAO:42|:36
- 1 - A 21 DFFE + 0 3 1 0 |SAO:42|:38
- 1 - A 23 DFFE + 0 3 1 0 |SAO:42|:40
- 2 - A 23 DFFE + 0 3 1 0 |SAO:42|:42
- 3 - A 23 DFFE + 0 1 1 0 |SAO:42|:44
- 1 - A 14 DFFE + 0 1 1 0 |SAO:42|:46
- 2 - A 24 DFFE + 0 1 1 0 |SAO:42|:48
- 1 - A 07 DFFE + 0 4 1 0 |SAO:42|:50
- 1 - A 01 DFFE + 0 4 1 0 |SAO:42|:52
- 3 - A 01 DFFE + 0 4 1 0 |SAO:42|:54
- 2 - A 01 DFFE + 0 4 1 0 |SAO:42|:56
- 3 - A 03 DFFE + 0 4 1 0 |SAO:42|:58
- 2 - A 03 DFFE + 0 4 1 0 |SAO:42|:60
- 1 - A 03 DFFE + 0 4 1 0 |SAO:42|:62
- 1 - A 05 DFFE + 0 2 1 0 |SAO:42|:64
- 4 - A 19 DFFE + 0 2 0 11 |SAO:42|count2 (|SAO:42|:66)
- 6 - A 13 DFFE + 0 1 0 13 |SAO:42|count1 (|SAO:42|:67)
- 2 - A 13 DFFE + 0 0 0 14 |SAO:42|count0 (|SAO:42|:68)
- 2 - A 21 AND2 0 3 0 8 |SAO:42|:395
- 1 - A 17 AND2 0 3 0 8 |SAO:42|:399
- 1 - A 15 AND2 0 3 0 8 |SAO:42|:403
- 3 - A 21 OR2 ! 0 3 0 5 |SAO:42|:407
- 8 - A 23 OR2 ! 0 3 0 10 |SAO:42|:415
- 4 - A 23 OR2 ! 0 3 0 7 |SAO:42|:419
- 2 - B 10 OR2 s 0 2 0 1 |SAO:42|~719~1
- 4 - B 22 OR2 s 0 3 0 1 |SAO:42|~719~2
- 2 - B 22 OR2 s 0 4 0 1 |SAO:42|~719~3
- 1 - B 10 OR2 s 0 4 0 1 |SAO:42|~719~4
- 6 - A 11 OR2 s 0 3 0 1 |SAO:42|~719~5
- 2 - A 11 OR2 ! 0 3 0 17 |SAO:42|:719
- 2 - B 20 OR2 ! 0 3 0 1 |SAO:42|:725
- 4 - B 20 OR2 ! 0 2 0 2 |SAO:42|:735
- 5 - B 20 OR2 ! 0 4 0 1 |SAO:42|:736
- 3 - B 20 OR2 ! 0 4 0 1 |SAO:42|:737
- 5 - A 20 OR2 ! 0 3 0 1 |SAO:42|:740
- 4 - A 20 OR2 ! 0 3 0 16 |SAO:42|:743
- 6 - B 13 OR2 s ! 0 3 0 1 |SAO:42|~767~1
- 7 - B 13 OR2 s ! 0 4 0 1 |SAO:42|~767~2
- 2 - B 04 AND2 s ! 0 2 0 2 |SAO:42|~767~3
- 1 - B 13 OR2 s ! 0 4 0 1 |SAO:42|~767~4
- 7 - A 20 OR2 s ! 0 3 0 1 |SAO:42|~767~5
- 1 - A 20 OR2 0 3 0 16 |SAO:42|:767
- 5 - A 23 OR2 s 0 3 0 10 |SAO:42|~784~1
- 3 - A 18 OR2 s ! 0 2 0 1 |SAO:42|~791~1
- 3 - B 19 OR2 s ! 0 2 0 3 |SAO:42|~791~2
- 5 - B 21 OR2 s ! 0 2 0 3 |SAO:42|~791~3
- 8 - B 14 OR2 s ! 0 3 0 1 |SAO:42|~791~4
- 7 - B 14 OR2 s ! 0 2 0 3 |SAO:42|~791~5
- 5 - B 14 OR2 s ! 0 4 0 1 |SAO:42|~791~6
- 2 - A 18 OR2 s ! 0 4 0 1 |SAO:42|~791~7
- 1 - A 18 OR2 0 3 0 15 |SAO:42|:791
- 1 - A 06 AND2 0 4 0 1 |SAO:42|:827
- 7 - A 10 OR2 s ! 0 2 0 1 |SAO:42|~851~1
- 8 - A 10 OR2 ! 0 4 0 2 |SAO:42|:856
- 5 - A 01 OR2 s ! 0 2 0 1 |SAO:42|~899~1
- 4 - A 02 AND2 0 4 0 2 |SAO:42|:947
- 2 - B 14 AND2 s 0 2 0 1 |SAO:42|~959~1
- 6 - A 23 AND2 s 0 3 0 2 |SAO:42|~959~2
- 3 - B 14 AND2 s 0 3 0 1 |SAO:42|~959~3
- 2 - B 24 AND2 s 0 4 0 1 |SAO:42|~959~4
- 6 - A 20 AND2 s 0 4 0 1 |SAO:42|~959~5
- 3 - A 20 AND2 s 0 4 0 1 |SAO:42|~959~6
- 8 - A 04 OR2 ! 0 4 0 4 |SAO:42|:959
- 2 - A 07 AND2 0 4 0 4 |SAO:42|:971
- 4 - A 10 OR2 s 0 4 0 1 |SAO:42|~1061~1
- 5 - A 10 OR2 s 0 4 0 1 |SAO:42|~1061~2
- 1 - A 10 OR2 0 4 0 1 |SAO:42|:1061
- 4 - B 10 OR2 s ! 0 3 0 2 |SAO:42|~1118~1
- 2 - B 13 OR2 s 0 4 0 1 |SAO:42|~1118~2
- 4 - B 13 OR2 s 0 4 0 1 |SAO:42|~1118~3
- 1 - B 14 OR2 s 0 4 0 1 |SAO:42|~1118~4
- 4 - B 14 OR2 s 0 4 0 1 |SAO:42|~1118~5
- 3 - B 13 OR2 s 0 4 0 1 |SAO:42|~1118~6
- 5 - B 13 OR2 s 0 4 0 1 |SAO:42|~1118~7
- 1 - B 20 OR2 s 0 4 0 1 |SAO:42|~1118~8
- 6 - B 14 OR2 s 0 3 0 1 |SAO:42|~1118~9
- 7 - B 20 OR2 s 0 4 0 1 |SAO:42|~1118~10
- 1 - B 24 OR2 s 0 4 0 1 |SAO:42|~1118~11
- 2 - A 20 OR2 s 0 4 0 1 |SAO:42|~1118~12
- 3 - A 10 OR2 s 0 4 0 1 |SAO:42|~1118~13
- 2 - A 10 OR2 s 0 4 0 1 |SAO:42|~1118~14
- 4 - A 01 OR2 s 0 4 0 1 |SAO:42|~1118~15
- 4 - A 03 OR2 0 4 0 1 |SAO:42|:1162
- 6 - A 10 OR2 s 0 4 0 1 |SAO:42|~1202~1
- 5 - A 03 OR2 0 4 0 1 |SAO:42|:1202
- 2 - A 12 OR2 s ! 0 3 0 2 |SAO:42|~1256~1
- 5 - C 15 AND2 0 3 0 1 |SPEED:39|LPM_ADD_SUB:120|addcore:adder|:59
- 4 - C 17 AND2 0 4 0 2 |SPEED:39|LPM_ADD_SUB:120|addcore:adder|:63
- 5 - C 17 OR2 0 4 0 2 |SPEED:39|LPM_ADD_SUB:120|addcore:adder|:78
- 7 - C 22 AND2 3 0 0 3 |SPEED:39|LPM_ADD_SUB:232|addcore:adder|:63
- 2 - C 01 DFFE + 1 2 0 28 |SPEED:39|tempclk (|SPEED:39|:15)
- 3 - C 17 DFFE + 2 2 0 3 |SPEED:39|count24 (|SPEED:39|:18)
- 2 - C 23 DFFE + 2 1 0 3 |SPEED:39|count23 (|SPEED:39|:19)
- 8 - C 15 DFFE + 2 1 0 3 |SPEED:39|count22 (|SPEED:39|:20)
- 6 - C 15 DFFE + 2 1 0 4 |SPEED:39|count21 (|SPEED:39|:21)
- 3 - C 16 DFFE + 2 2 0 5 |SPEED:39|count20 (|SPEED:39|:22)
- 6 - C 22 OR2 s ! 2 2 0 1 |SPEED:39|~61~1
- 1 - C 22 AND2 0 4 0 8 |SPEED:39|:61
- 3 - C 22 OR2 ! 2 2 0 1 |SPEED:39|:62
- 4 - C 22 OR2 ! 1 2 0 1 |SPEED:39|:63
- 5 - C 22 OR2 ! 3 1 0 1 |SPEED:39|:64
- 2 - C 22 AND2 2 1 0 7 |SPEED:39|:108
- 1 - C 17 OR2 0 4 0 2 |SPEED:39|:136
- 2 - C 15 OR2 0 4 0 2 |SPEED:39|:142
- 3 - C 15 OR2 0 4 0 2 |SPEED:39|:148
- 4 - C 15 OR2 0 3 0 1 |SPEED:39|:154
- 1 - C 15 AND2 s 0 4 0 1 |SPEED:39|~157~1
- 2 - C 17 OR2 0 4 0 1 |SPEED:39|:157
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:d:\ygcfile1\se-5m\test\file\top(sch)\spend\spendgdf.rpt
spendgdf
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 18/ 96( 18%) 17/ 48( 35%) 7/ 48( 14%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 12/ 96( 12%) 18/ 48( 37%) 26/ 48( 54%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 14/ 96( 14%) 17/ 48( 35%) 25/ 48( 52%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 5/24( 20%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 5/24( 20%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\ygcfile1\se-5m\test\file\top(sch)\spend\spendgdf.rpt
spendgdf
** CLOCK SIGNALS **
Type Fan-out Name
DFF 29 |SPEED:39|tempclk
INPUT 19 clk1024
INPUT 6 clk1
Device-Specific Information:d:\ygcfile1\se-5m\test\file\top(sch)\spend\spendgdf.rpt
spendgdf
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