legible.pl

viterbi译码器的一种fpga实现

#!/usr/sww/bin/perl

print "reparing the lines lengths\n";

chdir $ARGV[0];

$files = `echo *.v`;

foreach $file (split(/ /, $files)) {
    print "Changing verilog file : $file\n";
    open FILE, "<$file";
    open TMP, ">tmp";

	while (<FILE>) {
		$line = "";
		@parts = split(/,/, $_);
		$len = 0;
		for $part (@parts) {
			$len_part = length($part);
			if ($len + $len_part > 60) {
	#	print "len = $len_part , part = $part\n";
				print TMP "$line\n";
				$len = 0;
				$line = "";
			}
			$line .= "$part, ";
			$len += $len_part;
		}
		chop $line;
		chop $line;
		print TMP "$line";
	}

    close FILE;
    close TMP;
    system "cp tmp $file";
}