conf4

viterbi译码器的一种fpga实现

$code_rate = 2;  # rate = 1/code_rate
$K  = 4; 
$G[0] = 15;  # in decimal
$G[1] = 14;  # in decimal
$soft_dec = 3; 
$block_length = 12;  # > 4 * delay_elements (= 4 * K-1)
$W = 8; # it's not parameterizable yet
$block_part = 6; # both block_part and block_length / block_part must be integer
                 # CL for backtrack has length 2 * block_length
                 # CL for measurements has length block_part
                 # You get one result every block_length / block_part cycles
                 # The larger the block_part the larger the clock cycle


#$correct_pattern = "1011010100";
$correct_pattern = "101101010011111010100011101111111110101101001111101010111111111101001010100";