conf6

viterbi译码器的一种fpga实现

$code_rate = 2;  # rate = 1/code_rate
$K  = 6; 
$G[0] = 61;  # in decimal
$G[1] = 46;  # in decimal
$soft_dec = 3; 

$block_length = 30;  # > 4 * delay_elements (= 4 * K-1)

$correct_pattern = "1011010100";
#$correct_pattern = "101101010011111010100011101111111110101101001111101010111111111101001010100101101010011111010100011101111111110101101001111101010111111111101001010100101101010011111010100011101111111110101101001111101010111111111101001010100";