conf9

viterbi译码器的一种fpga实现

$code_rate = 2;  # rate = 1/code_rate
$K  = 9;
$G[0] = 369;  # in decimal
$G[1] = 483;  # in decimal
$soft_dec = 8;
$block_length = 32;  # > 4 * delay_elements (= 4 * K-1)
$block_part = 2;

#$correct_pattern = "101101010011010101010101011111111111000000000000111010101111111111110010100100100000011011101101010011010101010101011111111111000000000000111010101111111111110010100100100000011011101101010011010101010101011111111111000000000000111010101111111111110010100100100000011011101101010011010101010101011111111111000000000000111010101111111111110010100100100000011011";