viterbi_producer.pl

viterbi译码器的一种fpga实现

#!/usr/sww/bin/perl

#$delay_elements = "3,4,6,9";
$delay_elements = "3,4,6";
$max_acs = 256;

foreach $del_elem (split(/,/, $delay_elements)) {
	$min_block_length = 4 * $del_elem;
	$states_per_stage = 1 << $del_elem;

	for $i (0..6) {
	$block_length = int($min_block_length + (($i/2) * $min_block_length));
		for $stages (1..$block_length) {
			if ($block_length / $stages == int($block_length / $stages)) {
				$acs = $states_per_stage * $stages;
				if ($max_acs < $acs) {
#					print "conf : $del_elem, $block_length, $stages was rejected\n";
					next;
				}
				print "conf : $del_elem, $block_length, $stages was accepted\n";
				system "viterbi.pl $del_elem $block_length $stages";
			}
		}
	}
}