notes

viterbi译码器的一种fpga实现

results
-------

backtrack combinational logic length = 2 * block_part;
bit_lines_length = min(2 * block_part, block_length)

                                blk_len/blk_prt = int
block_length > 2 * block_part <========================> block_part = block_length. 
I could have left bit_line_length = 2 * block_part in this case and half of the bits 
would be valid (I had already implemented this special case so I left it).

valid outputs = block_length bits every (block_length / block_part)
							or 
				(block_length / block_part) / 2 invalid bit lines +
				(block_length / block_part) / 2 valid bit lines

				Note 1 : The above results may not be integers, meaning that there are output
				 bit lines where some of their bits are invalid and the others valid

				Note 2 : In the special case where block_part = block_length change 
				         "invalid bit lines" to "2 * block_part". In effect the general
				         expresion should have "backtrack combinational logic length" instead
						 of "invalid bit lines".

outputs order = inversed, meaning that the bit lines take the values of
				the MS bits of every block_length decoded bits first. 
				(bit_lines are also printed inversed therefore 2 inverses
				 to get the decoded output)


example :
decoded bits = 10101111
block_part = 2
block_length = 4

result :
bit_lines = 2
out : xx, xx,