altera_compatible.pl

来自「viterbi译码器的一种fpga实现」· PL 代码 · 共 29 行

#!/usr/sww/bin/perl

print "reparing the inputs and outputs in order to be compatible\n";
print "with MaxPlus. Changes : W = $ARGV[0], S = $ARGV[1]\n";

chdir $ARGV[2];
system "cp ../lib/* .";
system "cp ../run .";

$files = `echo *.v`;

foreach $file (split(/ /, $files)) {
	print "Changing verilog file : $file\n";
	open FILE, "<$file";
	open TMP, ">tmp";
	while (<FILE>) {
		if ((/output/) || (/input/)) {
			$_ =~ s/`W/$ARGV[0]/g;
			$_ =~ s/`S/$ARGV[1]/g;
		}
		print TMP;
	}
	close FILE;
	close TMP;
	system "cp tmp $file";
}