in_signal.v

来自「viterbi译码器的一种fpga实现」· Verilog 代码 · 共 161 行

    @(negedge reset)
		enc_bit01 = -4;
		enc_bit02 = -4;
		enc_bit11 = -4;
		enc_bit12 = 3;
		enc_bit21 = 3;
		enc_bit22 = 3;
		enc_bit31 = 3;
		enc_bit32 = -4;
		enc_bit41 = 3;
		enc_bit42 = -4;
		enc_bit51 = 3;
		enc_bit52 = 3;
		enc_bit61 = -4;
		enc_bit62 = 3;
		enc_bit71 = 3;
		enc_bit72 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = -4;
		enc_bit21 = -4;
		enc_bit22 = -4;
		enc_bit31 = 3;
		enc_bit32 = -4;
		enc_bit41 = -4;
		enc_bit42 = 3;
		enc_bit51 = -4;
		enc_bit52 = 3;
		enc_bit61 = -4;
		enc_bit62 = 3;
		enc_bit71 = 3;
		enc_bit72 = -4;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
		enc_bit21 = 3;
		enc_bit22 = 3;
		enc_bit31 = -4;
		enc_bit32 = 3;
		enc_bit41 = -4;
		enc_bit42 = -4;
		enc_bit51 = 3;
		enc_bit52 = 3;
		enc_bit61 = -4;
		enc_bit62 = -4;
		enc_bit71 = 3;
		enc_bit72 = -4;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = -4;
		enc_bit21 = 3;
		enc_bit22 = 3;
		enc_bit31 = 3;
		enc_bit32 = -4;
		enc_bit41 = -4;
		enc_bit42 = 3;
		enc_bit51 = -4;
		enc_bit52 = 3;
		enc_bit61 = -4;
		enc_bit62 = 3;
		enc_bit71 = -4;
		enc_bit72 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
		enc_bit21 = -4;
		enc_bit22 = 3;
		enc_bit31 = 3;
		enc_bit32 = -4;
		enc_bit41 = 3;
		enc_bit42 = 3;
		enc_bit51 = -4;
		enc_bit52 = 3;
		enc_bit61 = 3;
		enc_bit62 = 3;
		enc_bit71 = 3;
		enc_bit72 = -4;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = -4;
		enc_bit11 = 3;
		enc_bit12 = 3;
		enc_bit21 = -4;
		enc_bit22 = 3;
		enc_bit31 = -4;
		enc_bit32 = -4;
		enc_bit41 = -4;
		enc_bit42 = -4;
		enc_bit51 = 3;
		enc_bit52 = -4;
		enc_bit61 = -4;
		enc_bit62 = 3;
		enc_bit71 = -4;
		enc_bit72 = 3;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = 3;
		enc_bit12 = -4;
		enc_bit21 = 3;
		enc_bit22 = 3;
		enc_bit31 = -4;
		enc_bit32 = 3;
		enc_bit41 = 3;
		enc_bit42 = 3;
		enc_bit51 = -4;
		enc_bit52 = 3;
		enc_bit61 = 3;
		enc_bit62 = 3;
		enc_bit71 = 3;
		enc_bit72 = -4;
	@(posedge clk)
		enc_bit01 = -4;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
		enc_bit21 = -4;
		enc_bit22 = 3;
		enc_bit31 = -4;
		enc_bit32 = 3;
		enc_bit41 = -4;
		enc_bit42 = 3;
		enc_bit51 = -4;
		enc_bit52 = 3;
		enc_bit61 = -4;
		enc_bit62 = 3;
		enc_bit71 = -4;
		enc_bit72 = 3;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = -4;
		enc_bit11 = 3;
		enc_bit12 = 3;
		enc_bit21 = -4;
		enc_bit22 = 3;
		enc_bit31 = -4;
		enc_bit32 = -4;
		enc_bit41 = -4;
		enc_bit42 = -4;
		enc_bit51 = -4;
		enc_bit52 = 3;
		enc_bit61 = 3;
		enc_bit62 = 3;
		enc_bit71 = -4;
		enc_bit72 = 3;
	@(posedge clk)
		enc_bit01 = 3;
		enc_bit02 = 3;
		enc_bit11 = -4;
		enc_bit12 = 3;
		enc_bit21 = -4;
		enc_bit22 = -4;