block.v

viterbi译码器的一种fpga实现

`include "defs.h"

module block(sum_enc_bits0,  sub_enc_bits0,  sum_enc_bits1, 
 sub_enc_bits1,  sum_enc_bits2,  sub_enc_bits2,  
             sum_enc_bits3,  sub_enc_bits3,  sum_enc_bits4, 
 sub_enc_bits4,  sum_enc_bits5,  sub_enc_bits5,  
             sum_enc_bits6,  sub_enc_bits6,  sum_enc_bits7, 
 sub_enc_bits7,  cmp,  reset,  clk);

input            reset,  clk;
input   [4-1:0] sum_enc_bits0,  sub_enc_bits0,  sum_enc_bits1, 
 sub_enc_bits1,  sum_enc_bits2,  sub_enc_bits2,  
             sum_enc_bits3,  sub_enc_bits3,  sum_enc_bits4, 
 sub_enc_bits4,  sum_enc_bits5,  sub_enc_bits5,  
             sum_enc_bits6,  sub_enc_bits6,  sum_enc_bits7, 
 sub_enc_bits7;
output  [32-1:0] cmp;
wire    [`W-1:0] out000,  out001,  out010,  out011,  out020,  out021, 
 out030,  out031, 
                 out100,  out101,  out110,  out111,  out120,  out121, 
 out130,  out131, 
                 out200,  out201,  out210,  out211,  out220,  out221, 
 out230,  out231, 
                 out300,  out301,  out310,  out311,  out320,  out321, 
 out330,  out331, 
                 out400,  out401,  out410,  out411,  out420,  out421, 
 out430,  out431, 
                 out500,  out501,  out510,  out511,  out520,  out521, 
 out530,  out531, 
                 out600,  out601,  out610,  out611,  out620,  out621, 
 out630,  out631, 
                 out700,  out701,  out710,  out711,  out720,  out721, 
 out730,  out731;
reg     [`W-1:0] ns700,  ns701,  ns710,  ns711,  ns720,  ns721,  ns730, 
 ns731;

stage  st0(ns700,  ns711,  ns730,  ns721,  ns710,  ns701,  ns720,  ns731, 
         sum_enc_bits0,  sub_enc_bits0, 
         out000,  out001,  out010,  out011,  out020,  out021,  out030, 
 out031,  cmp[3:0]);
stage  st1(out000,  out011,  out030,  out021,  out010,  out001,  out020, 
 out031, 
         sum_enc_bits1,  sub_enc_bits1, 
         out100,  out101,  out110,  out111,  out120,  out121,  out130, 
 out131,  cmp[7:4]);
stage  st2(out100,  out111,  out130,  out121,  out110,  out101,  out120, 
 out131, 
         sum_enc_bits2,  sub_enc_bits2, 
         out200,  out201,  out210,  out211,  out220,  out221,  out230, 
 out231,  cmp[11:8]);
stage  st3(out200,  out211,  out230,  out221,  out210,  out201,  out220, 
 out231, 
         sum_enc_bits3,  sub_enc_bits3, 
         out300,  out301,  out310,  out311,  out320,  out321,  out330, 
 out331,  cmp[15:12]);
stage  st4(out300,  out311,  out330,  out321,  out310,  out301,  out320, 
 out331, 
         sum_enc_bits4,  sub_enc_bits4, 
         out400,  out401,  out410,  out411,  out420,  out421,  out430, 
 out431,  cmp[19:16]);
stage  st5(out400,  out411,  out430,  out421,  out410,  out401,  out420, 
 out431, 
         sum_enc_bits5,  sub_enc_bits5, 
         out500,  out501,  out510,  out511,  out520,  out521,  out530, 
 out531,  cmp[23:20]);
stage  st6(out500,  out511,  out530,  out521,  out510,  out501,  out520, 
 out531, 
         sum_enc_bits6,  sub_enc_bits6, 
         out600,  out601,  out610,  out611,  out620,  out621,  out630, 
 out631,  cmp[27:24]);
stage  st7(out600,  out611,  out630,  out621,  out610,  out601,  out620, 
 out631, 
         sum_enc_bits7,  sub_enc_bits7, 
         out700,  out701,  out710,  out711,  out720,  out721,  out730, 
 out731,  cmp[31:28]);

       always @(posedge clk)
                {ns700,  ns701,  ns710,  ns711,  ns720,  ns721,  ns730, 
 ns731} = 
                reset ? {8'h64,  120'b0} : 
                {out700,  out701,  out710,  out711,  out720,  out721, 
 out730,  out731};

endmodule