todo

viterbi译码器的一种fpga实现

1. Automatic input/output                 Done
2. Merge bits creating buses.             Done
3. Create the decoder.v file.             Done
4. Automatic generation of decoder.v / testing code  Done
5. Test different viterbi decoders whether they work Done
6. Delete "id" Done
7. Make it sithesizable for Maxplus Done