acs1_0.v

来自「viterbi译码器的一种fpga实现」· Verilog 代码 · 共 26 行

//Actually the node is a CSA and not an ACS.
`include "defs.h"

module ACS1_0(metric0, metric1, 
			sum_enc_bits,  
			new_metric0, new_metric1, compare);

input   [`W-1:0] metric0, metric1;
input   [`S-1:0] sum_enc_bits;
output  [`W-1:0] new_metric0, new_metric1;
output  compare;


wire   [`W-1:0] sub_metrs = ~metric0 + metric1;
wire   compare = sub_metrs[`W-1];
wire   [`W-1:0] survival = (compare == 1 ? metric0 : metric1);

wire   [`S-1:0] metric_change = sum_enc_bits;  // metric change
wire   [`W-1:0] signext_m = {{`W-`S{metric_change[`S-1]}}, metric_change};
assign new_metric0 = survival + signext_m;
assign new_metric1 = survival - signext_m;

endmodule