decoder_time_post.vhd

16b20b编解码VHDL代码.

  signal upper_dec_jin_MC_D : STD_LOGIC; 
  signal serial_data_10_II_UIM : STD_LOGIC; 
  signal upper_dec_jin_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_dec_jin_MC_D1 : STD_LOGIC; 
  signal upper_dec_jin_MC_D2 : STD_LOGIC; 
  signal upper_dec_fin_MC_Q : STD_LOGIC; 
  signal upper_dec_fin_MC_D : STD_LOGIC; 
  signal serial_data_13_II_UIM : STD_LOGIC; 
  signal upper_dec_fin_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_dec_fin_MC_D1 : STD_LOGIC; 
  signal upper_dec_fin_MC_D2 : STD_LOGIC; 
  signal N_PZ_189_MC_Q : STD_LOGIC; 
  signal N_PZ_189_MC_D : STD_LOGIC; 
  signal upper_dec_iin : STD_LOGIC; 
  signal upper_dec_ein : STD_LOGIC; 
  signal N_PZ_305 : STD_LOGIC; 
  signal N_PZ_189_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_189_MC_D1 : STD_LOGIC; 
  signal N_PZ_189_MC_D2 : STD_LOGIC; 
  signal upper_dec_iin_MC_Q : STD_LOGIC; 
  signal upper_dec_iin_MC_D : STD_LOGIC; 
  signal serial_data_14_II_UIM : STD_LOGIC; 
  signal upper_dec_iin_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_dec_iin_MC_D1 : STD_LOGIC; 
  signal upper_dec_iin_MC_D2 : STD_LOGIC; 
  signal upper_dec_ein_MC_Q : STD_LOGIC; 
  signal upper_dec_ein_MC_D : STD_LOGIC; 
  signal serial_data_15_II_UIM : STD_LOGIC; 
  signal upper_dec_ein_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_dec_ein_MC_D1 : STD_LOGIC; 
  signal upper_dec_ein_MC_D2 : STD_LOGIC; 
  signal N_PZ_305_MC_Q : STD_LOGIC; 
  signal N_PZ_305_MC_D : STD_LOGIC; 
  signal upper_dec_din : STD_LOGIC; 
  signal upper_dec_cin : STD_LOGIC; 
  signal N_PZ_305_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_305_MC_D1 : STD_LOGIC; 
  signal N_PZ_305_MC_D2 : STD_LOGIC; 
  signal upper_dec_din_MC_Q : STD_LOGIC; 
  signal upper_dec_din_MC_D : STD_LOGIC; 
  signal serial_data_16_II_UIM : STD_LOGIC; 
  signal upper_dec_din_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_dec_din_MC_D1 : STD_LOGIC; 
  signal upper_dec_din_MC_D2 : STD_LOGIC; 
  signal upper_dec_cin_MC_Q : STD_LOGIC; 
  signal upper_dec_cin_MC_D : STD_LOGIC; 
  signal serial_data_17_II_UIM : STD_LOGIC; 
  signal upper_dec_cin_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_dec_cin_MC_D1 : STD_LOGIC; 
  signal upper_dec_cin_MC_D2 : STD_LOGIC; 
  signal upper_dec_gin_MC_Q : STD_LOGIC; 
  signal upper_dec_gin_MC_D : STD_LOGIC; 
  signal serial_data_12_II_UIM : STD_LOGIC; 
  signal upper_dec_gin_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_dec_gin_MC_D1 : STD_LOGIC; 
  signal upper_dec_gin_MC_D2 : STD_LOGIC; 
  signal decoded_data_11_MC_Q : STD_LOGIC; 
  signal decoded_data_11_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_11_MC_D : STD_LOGIC; 
  signal upper_dec_eout : STD_LOGIC; 
  signal decoded_data_11_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_11_MC_D1 : STD_LOGIC; 
  signal decoded_data_11_MC_D2 : STD_LOGIC; 
  signal decoded_data_11_MC_UIM : STD_LOGIC; 
  signal upper_dec_eout_MC_Q : STD_LOGIC; 
  signal upper_dec_eout_MC_D : STD_LOGIC; 
  signal upper_dec_eout_MC_D1 : STD_LOGIC; 
  signal upper_dec_eout_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_298 : STD_LOGIC; 
  signal N_PZ_308 : STD_LOGIC; 
  signal N_PZ_302 : STD_LOGIC; 
  signal upper_dec_eout_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_dec_ain : STD_LOGIC; 
  signal upper_dec_eout_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_343 : STD_LOGIC; 
  signal upper_dec_eout_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_dec_bin : STD_LOGIC; 
  signal N_PZ_348 : STD_LOGIC; 
  signal upper_dec_eout_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_dec_eout_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_dec_eout_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_dec_eout_MC_D2_PT_7 : STD_LOGIC; 
  signal upper_dec_eout_MC_D2_PT_8 : STD_LOGIC; 
  signal upper_dec_eout_MC_D2_PT_9 : STD_LOGIC; 
  signal upper_dec_eout_MC_D2 : STD_LOGIC; 
  signal N_PZ_298_MC_Q : STD_LOGIC; 
  signal N_PZ_298_MC_D : STD_LOGIC; 
  signal N_PZ_298_MC_D1 : STD_LOGIC; 
  signal N_PZ_298_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_298_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_298_MC_D2 : STD_LOGIC; 
  signal upper_dec_bin_MC_Q : STD_LOGIC; 
  signal upper_dec_bin_MC_D : STD_LOGIC; 
  signal serial_data_18_II_UIM : STD_LOGIC; 
  signal upper_dec_bin_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_dec_bin_MC_D1 : STD_LOGIC; 
  signal upper_dec_bin_MC_D2 : STD_LOGIC; 
  signal N_PZ_308_MC_Q : STD_LOGIC; 
  signal N_PZ_308_MC_D : STD_LOGIC; 
  signal N_PZ_308_MC_D1 : STD_LOGIC; 
  signal N_PZ_308_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_308_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_308_MC_D2 : STD_LOGIC; 
  signal upper_dec_ain_MC_Q : STD_LOGIC; 
  signal upper_dec_ain_MC_D : STD_LOGIC; 
  signal serial_data_19_II_UIM : STD_LOGIC; 
  signal upper_dec_ain_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_dec_ain_MC_D1 : STD_LOGIC; 
  signal upper_dec_ain_MC_D2 : STD_LOGIC; 
  signal N_PZ_302_MC_Q : STD_LOGIC; 
  signal N_PZ_302_MC_D : STD_LOGIC; 
  signal N_PZ_302_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_302_MC_D1 : STD_LOGIC; 
  signal N_PZ_302_MC_D2 : STD_LOGIC; 
  signal N_PZ_343_MC_Q : STD_LOGIC; 
  signal N_PZ_343_MC_D : STD_LOGIC; 
  signal N_PZ_343_MC_D1 : STD_LOGIC; 
  signal N_PZ_343_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_343_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_343_MC_D2 : STD_LOGIC; 
  signal N_PZ_348_MC_Q : STD_LOGIC; 
  signal N_PZ_348_MC_D : STD_LOGIC; 
  signal N_PZ_348_MC_D1 : STD_LOGIC; 
  signal N_PZ_348_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_348_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_348_MC_D2 : STD_LOGIC; 
  signal decoded_data_12_MC_Q : STD_LOGIC; 
  signal decoded_data_12_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_12_MC_D : STD_LOGIC; 
  signal upper_dec_dout : STD_LOGIC; 
  signal decoded_data_12_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_12_MC_D1 : STD_LOGIC; 
  signal decoded_data_12_MC_D2 : STD_LOGIC; 
  signal decoded_data_12_MC_UIM : STD_LOGIC; 
  signal upper_dec_dout_MC_Q : STD_LOGIC; 
  signal upper_dec_dout_MC_D : STD_LOGIC; 
  signal upper_dec_dout_MC_D1 : STD_LOGIC; 
  signal upper_dec_dout_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_dec_dout_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_dec_dout_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_dec_dout_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_dec_dout_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_dec_dout_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_dec_dout_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_dec_dout_MC_D2 : STD_LOGIC; 
  signal decoded_data_13_MC_Q : STD_LOGIC; 
  signal decoded_data_13_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_13_MC_D : STD_LOGIC; 
  signal upper_dec_cout : STD_LOGIC; 
  signal decoded_data_13_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_13_MC_D1 : STD_LOGIC; 
  signal decoded_data_13_MC_D2 : STD_LOGIC; 
  signal decoded_data_13_MC_UIM : STD_LOGIC; 
  signal upper_dec_cout_MC_Q : STD_LOGIC; 
  signal upper_dec_cout_MC_D : STD_LOGIC; 
  signal upper_dec_cout_MC_D1 : STD_LOGIC; 
  signal upper_dec_cout_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_dec_cout_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_dec_cout_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_dec_cout_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_dec_cout_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_dec_cout_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_dec_cout_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_dec_cout_MC_D2_PT_7 : STD_LOGIC; 
  signal upper_dec_cout_MC_D2_PT_8 : STD_LOGIC; 
  signal upper_dec_cout_MC_D2 : STD_LOGIC; 
  signal decoded_data_14_MC_Q : STD_LOGIC; 
  signal decoded_data_14_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_14_MC_D : STD_LOGIC; 
  signal upper_dec_bout : STD_LOGIC; 
  signal decoded_data_14_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_14_MC_D1 : STD_LOGIC; 
  signal decoded_data_14_MC_D2 : STD_LOGIC; 
  signal decoded_data_14_MC_UIM : STD_LOGIC; 
  signal upper_dec_bout_MC_Q : STD_LOGIC; 
  signal upper_dec_bout_MC_D : STD_LOGIC; 
  signal upper_dec_bout_MC_D1 : STD_LOGIC; 
  signal upper_dec_bout_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_dec_bout_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_dec_bout_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_dec_bout_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_dec_bout_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_dec_bout_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_dec_bout_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_dec_bout_MC_D2_PT_7 : STD_LOGIC; 
  signal upper_dec_bout_MC_D2_PT_8 : STD_LOGIC; 
  signal upper_dec_bout_MC_D2 : STD_LOGIC; 
  signal decoded_data_15_MC_Q : STD_LOGIC; 
  signal decoded_data_15_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_15_MC_D : STD_LOGIC; 
  signal upper_dec_aout : STD_LOGIC; 
  signal decoded_data_15_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_15_MC_D1 : STD_LOGIC; 
  signal decoded_data_15_MC_D2 : STD_LOGIC; 
  signal decoded_data_15_MC_UIM : STD_LOGIC; 
  signal upper_dec_aout_MC_Q : STD_LOGIC; 
  signal upper_dec_aout_MC_D : STD_LOGIC; 
  signal upper_dec_aout_MC_D1 : STD_LOGIC; 
  signal upper_dec_aout_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_dec_aout_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_dec_aout_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_dec_aout_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_dec_aout_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_dec_aout_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_dec_aout_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_dec_aout_MC_D2_PT_7 : STD_LOGIC; 
  signal upper_dec_aout_MC_D2 : STD_LOGIC; 
  signal decoded_data_1_MC_Q : STD_LOGIC; 
  signal decoded_data_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_1_MC_D : STD_LOGIC; 
  signal lower_dec_gout : STD_LOGIC; 
  signal decoded_data_1_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_1_MC_D1 : STD_LOGIC; 
  signal decoded_data_1_MC_D2 : STD_LOGIC; 
  signal decoded_data_1_MC_UIM : STD_LOGIC; 
  signal lower_dec_gout_MC_Q : STD_LOGIC; 
  signal lower_dec_gout_MC_D : STD_LOGIC; 
  signal lower_dec_gout_MC_D1 : STD_LOGIC; 
  signal lower_dec_gout_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_gout_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_gout_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_dec_gout_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_dec_gout_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_dec_gout_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_dec_gout_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_dec_gout_MC_D2 : STD_LOGIC; 
  signal decoded_data_2_MC_Q : STD_LOGIC; 
  signal decoded_data_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_2_MC_D : STD_LOGIC; 
  signal lower_dec_fout : STD_LOGIC; 
  signal decoded_data_2_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_2_MC_D1 : STD_LOGIC; 
  signal decoded_data_2_MC_D2 : STD_LOGIC; 
  signal decoded_data_2_MC_UIM : STD_LOGIC; 
  signal lower_dec_fout_MC_Q : STD_LOGIC; 
  signal lower_dec_fout_MC_D : STD_LOGIC; 
  signal lower_dec_fout_MC_D1 : STD_LOGIC; 
  signal lower_dec_fout_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_fout_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_fout_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_dec_fout_MC_D2_PT_3 : STD_LOGIC;