encoder_time_post.vhd

16b20b编解码VHDL代码.

  signal upper_enc_enc_8b_10b_prs_state_fft2_MC_D2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft2_MC_D_TFF : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft3_MC_Q : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft3_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft3_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft3_MC_D1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft3_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft3_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft3_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft3_MC_D2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft3_MC_D_TFF : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft1_MC_Q : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft1_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft1_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft1_MC_D1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft1_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft1_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft1_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft1_MC_D2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_fft1_MC_D_TFF : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd1_MC_Q : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd1_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd1_MC_D : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd1_MC_D1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd1_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd1_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd1_MC_D2 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd2_MC_Q : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd2_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd2_MC_D : STD_LOGIC; 
  signal N_PZ_312 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd2_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd2_MC_D1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_ffd2_MC_D2 : STD_LOGIC; 
  signal N_PZ_312_MC_Q : STD_LOGIC; 
  signal N_PZ_312_MC_D : STD_LOGIC; 
  signal N_PZ_312_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_312_MC_D1 : STD_LOGIC; 
  signal N_PZ_312_MC_D2 : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_Q : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D1 : STD_LOGIC; 
  signal N_PZ_307 : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_nds6 : STD_LOGIC; 
  signal lower_enc_pds6 : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D2_PT_2 : STD_LOGIC; 
  signal data_trs_5_II_UIM : STD_LOGIC; 
  signal data_trs_6_II_UIM : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D2_PT_3 : STD_LOGIC; 
  signal data_trs_7_II_UIM : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_enc_dis_func_n0040_MC_D2 : STD_LOGIC; 
  signal N_PZ_307_MC_Q : STD_LOGIC; 
  signal N_PZ_307_MC_D : STD_LOGIC; 
  signal run_disparity : STD_LOGIC; 
  signal N_PZ_307_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_307_MC_D1 : STD_LOGIC; 
  signal N_PZ_307_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_307_MC_D2 : STD_LOGIC; 
  signal run_disparity_MC_Q : STD_LOGIC; 
  signal run_disparity_MC_D : STD_LOGIC; 
  signal dis_in_II_UIM : STD_LOGIC; 
  signal run_disparity_MC_D1_PT_0 : STD_LOGIC; 
  signal run_disparity_MC_D1 : STD_LOGIC; 
  signal upper_enc_nds6 : STD_LOGIC; 
  signal upper_enc_pds6 : STD_LOGIC; 
  signal run_disparity_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_327 : STD_LOGIC; 
  signal run_disparity_MC_D2_PT_1 : STD_LOGIC; 
  signal run_disparity_MC_D2_PT_2 : STD_LOGIC; 
  signal run_disparity_MC_D2_PT_3 : STD_LOGIC; 
  signal run_disparity_MC_D2 : STD_LOGIC; 
  signal upper_enc_nds6_MC_Q : STD_LOGIC; 
  signal upper_enc_nds6_MC_D : STD_LOGIC; 
  signal upper_enc_nds6_MC_D1 : STD_LOGIC; 
  signal upper_enc_nds6_MC_D2_PT_0 : STD_LOGIC; 
  signal data_trs_11_II_UIM : STD_LOGIC; 
  signal data_trs_12_II_UIM : STD_LOGIC; 
  signal N_PZ_246 : STD_LOGIC; 
  signal upper_enc_nds6_MC_D2_PT_1 : STD_LOGIC; 
  signal data_trs_10_II_UIM : STD_LOGIC; 
  signal data_trs_8_II_UIM : STD_LOGIC; 
  signal data_trs_9_II_UIM : STD_LOGIC; 
  signal upper_enc_nds6_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_317 : STD_LOGIC; 
  signal upper_enc_nds6_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_enc_nds6_MC_D2 : STD_LOGIC; 
  signal N_PZ_246_MC_Q : STD_LOGIC; 
  signal N_PZ_246_MC_D : STD_LOGIC; 
  signal N_PZ_246_MC_D1 : STD_LOGIC; 
  signal N_PZ_246_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_246_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_246_MC_D2 : STD_LOGIC; 
  signal N_PZ_317_MC_Q : STD_LOGIC; 
  signal N_PZ_317_MC_D : STD_LOGIC; 
  signal N_PZ_317_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_317_MC_D1 : STD_LOGIC; 
  signal N_PZ_317_MC_D2 : STD_LOGIC; 
  signal upper_enc_pds6_MC_Q : STD_LOGIC; 
  signal upper_enc_pds6_MC_D : STD_LOGIC; 
  signal upper_enc_pds6_MC_D1 : STD_LOGIC; 
  signal upper_enc_pds6_MC_D2_PT_0 : STD_LOGIC; 
  signal k_char_II_UIM : STD_LOGIC; 
  signal upper_enc_pds6_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_pds6_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_pds6_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_enc_pds6_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_enc_pds6_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_enc_pds6_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_enc_pds6_MC_D2 : STD_LOGIC; 
  signal N_PZ_327_MC_Q : STD_LOGIC; 
  signal N_PZ_327_MC_D : STD_LOGIC; 
  signal N_PZ_327_MC_D1 : STD_LOGIC; 
  signal data_trs_13_II_UIM : STD_LOGIC; 
  signal data_trs_14_II_UIM : STD_LOGIC; 
  signal N_PZ_327_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_327_MC_D2_PT_1 : STD_LOGIC; 
  signal data_trs_15_II_UIM : STD_LOGIC; 
  signal N_PZ_327_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_327_MC_D2 : STD_LOGIC; 
  signal lower_enc_nds6_MC_Q : STD_LOGIC; 
  signal lower_enc_nds6_MC_D : STD_LOGIC; 
  signal lower_enc_nds6_MC_D1 : STD_LOGIC; 
  signal lower_enc_nds6_MC_D2_PT_0 : STD_LOGIC; 
  signal data_trs_3_II_UIM : STD_LOGIC; 
  signal data_trs_4_II_UIM : STD_LOGIC; 
  signal N_PZ_342 : STD_LOGIC; 
  signal lower_enc_nds6_MC_D2_PT_1 : STD_LOGIC; 
  signal data_trs_0_II_UIM : STD_LOGIC; 
  signal data_trs_1_II_UIM : STD_LOGIC; 
  signal data_trs_2_II_UIM : STD_LOGIC; 
  signal lower_enc_nds6_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_nds6_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_nds6_MC_D2 : STD_LOGIC; 
  signal N_PZ_342_MC_Q : STD_LOGIC; 
  signal N_PZ_342_MC_D : STD_LOGIC; 
  signal N_PZ_342_MC_D1 : STD_LOGIC; 
  signal N_PZ_342_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_342_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_342_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_342_MC_D2 : STD_LOGIC; 
  signal lower_enc_pds6_MC_Q : STD_LOGIC; 
  signal lower_enc_pds6_MC_D : STD_LOGIC; 
  signal lower_enc_pds6_MC_D1 : STD_LOGIC; 
  signal lower_enc_pds6_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_pds6_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_pds6_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_pds6_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_pds6_MC_D2 : STD_LOGIC; 
  signal frame_out_enc_MC_Q : STD_LOGIC; 
  signal frame_out_enc_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal frame_out_enc_MC_D : STD_LOGIC; 
  signal frame_out_enc_MC_D1_PT_0 : STD_LOGIC; 
  signal frame_out_enc_MC_D1 : STD_LOGIC; 
  signal frame_out_enc_MC_D2 : STD_LOGIC; 
  signal serial_data_0_MC_Q : STD_LOGIC; 
  signal serial_data_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal serial_data_0_MC_D : STD_LOGIC; 
  signal serial_data_0_MC_D1 : STD_LOGIC; 
  signal serial_data_0_MC_UIM : STD_LOGIC; 
  signal serial_data_0_MC_D2_PT_0 : STD_LOGIC; 
  signal serial_data_0_MC_D2_PT_1 : STD_LOGIC; 
  signal serial_data_0_MC_D2_PT_2 : STD_LOGIC; 
  signal serial_data_0_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_s_term : STD_LOGIC; 
  signal serial_data_0_MC_D2_PT_4 : STD_LOGIC; 
  signal serial_data_0_MC_D2 : STD_LOGIC; 
  signal lower_enc_s_term_MC_Q : STD_LOGIC; 
  signal lower_enc_s_term_MC_D : STD_LOGIC; 
  signal lower_enc_s_term_MC_D1 : STD_LOGIC; 
  signal N_PZ_377 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_9 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_10 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2_PT_11 : STD_LOGIC; 
  signal lower_enc_s_term_MC_D2 : STD_LOGIC; 
  signal N_PZ_377_MC_Q : STD_LOGIC; 
  signal N_PZ_377_MC_D : STD_LOGIC; 
  signal N_PZ_377_MC_D1 : STD_LOGIC; 
  signal N_PZ_377_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_377_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_377_MC_D2 : STD_LOGIC; 
  signal serial_data_10_MC_Q : STD_LOGIC; 
  signal serial_data_10_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal serial_data_10_MC_D : STD_LOGIC; 
  signal serial_data_10_MC_D1 : STD_LOGIC; 
  signal serial_data_10_MC_UIM : STD_LOGIC; 
  signal serial_data_10_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_302 : STD_LOGIC; 
  signal serial_data_10_MC_D2_PT_1 : STD_LOGIC; 
  signal serial_data_10_MC_D2_PT_2 : STD_LOGIC; 
  signal serial_data_10_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_enc_s_term : STD_LOGIC; 
  signal serial_data_10_MC_D2_PT_4 : STD_LOGIC; 
  signal serial_data_10_MC_D2 : STD_LOGIC; 
  signal N_PZ_302_MC_Q : STD_LOGIC; 
  signal N_PZ_302_MC_D : STD_LOGIC; 
  signal N_PZ_302_MC_D1 : STD_LOGIC; 
  signal N_PZ_302_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_302_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_302_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_302_MC_D2 : STD_LOGIC; 
  signal upper_enc_s_term_MC_Q : STD_LOGIC; 
  signal upper_enc_s_term_MC_D : STD_LOGIC; 
  signal upper_enc_s_term_MC_D1 : STD_LOGIC; 
  signal upper_enc_s_term_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_s_term_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_s_term_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_s_term_MC_D2_PT_3 : STD_LOGIC;