encoder.npl

16b20b编解码VHDL代码.

JDF F
// Created by Project Navigator ver 1.0
PROJECT Encoder_16b20b
DESIGN encoder Normal
DEVFAM xpla3
DEVFAMTIME 315558000
DEVICE xcr3128xl
DEVICETIME 315558000
DEVPKG VQ100
DEVPKGTIME 315558000
DEVSPEED -6
DEVSPEEDTIME 315558000
FLOW XST VHDL
FLOWTIME 315558000
STIMULUS main_tb.vhd Normal
MODULE encoder.vhd
MODSTYLE enc_16b20b Normal
MODULE dis_gen_low.vhd
MODSTYLE dis_gen_low Normal
MODULE main_enc_up.vhd
MODSTYLE encoder_up Normal
MODULE dis_gen_up.vhd
MODSTYLE dis_gen_up Normal
MODULE s_gen.vhd
MODSTYLE s_gen Normal
MODULE enc_func.vhd
MODSTYLE enc_func Normal
MODULE main_enc_low.vhd
MODSTYLE encoder_low Normal
LIBFILE pkg_convert.vhd work ***
LIBFILE pkg_spc_char.vhd work ***
[Normal]
p_ModelSimSimRunTime_tbw=xstvhd, xpla3, Module Bencher Waveform.t_MSimulateBehavioralVhdlModel, 315558000, 1000ns
p_PostParSimModelName=xstvhd, xpla3, VHDL.t_fitDes, 1040937908, ENCODER_TIME_POST
p_SimModelRenTopLevEntTo=xstvhd, xpla3, VHDL.t_fitDes, 1040937908, ENCODER_TIME_POST
p_VhdlSimDesignUnitName_behav=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1040937849, main_tb
p_VhdlSimDesignUnitName_postPar=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1040937868, main_tb_post
_VhdlSimCustom_behav=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1040937849, func_sim.do
_VhdlSimCustom_postPar=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1040937868, post_sim.do
_VhdlSimDo_behav=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1040937849, False
_VhdlSimDo_postPar=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1040937868, False
[STRATEGY-LIST]
Normal=True