decoder_time_post.vhd

16b20b编解码VHDL代码.

  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_8_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_7_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_aout_MC_D2_PT_7_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_5_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_6_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_gout_MC_D2_PT_6_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_6_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_6_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_fout_MC_D2_PT_6_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_6_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_7_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_7_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_7_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_8_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_8_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_8_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_9_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_9_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_9_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_eout_MC_D2_PT_9_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003561_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003561_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003561_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003561_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003561_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003561_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003561_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_180_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_180_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003564_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003564_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003574_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003574_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_n003574_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_5_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_7_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_7_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_8_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_8_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_9_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_9_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_10_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_10_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_10_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dout_MC_D2_PT_10_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_5_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_6_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_7_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_7_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_cout_MC_D2_PT_8_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_6_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_7_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_7_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_8_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_8_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_8_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_9_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_9_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_bout_MC_D2_PT_9_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_6_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_7_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_7_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_8_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_8_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_9_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_aout_MC_D2_PT_9_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_7_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_7_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hout_MC_D2_PT_8_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_ill_char_det_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_err_prs_state_ffd1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_err_prs_state_ffd1_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_err_ill_char_det7_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_err_ill_char_det7_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_err_ill_char_det7_MC_D2_PT