decoder_time_post.vhd

16b20b编解码VHDL代码.

  signal err_ill_char_det7_MC_D2_PT_14 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_15 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_16 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_17 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_18 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_19 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2 : STD_LOGIC; 
  signal err_n0020_MC_Q : STD_LOGIC; 
  signal err_n0020_MC_D : STD_LOGIC; 
  signal lower_dec_k_dec : STD_LOGIC; 
  signal err_n0020_MC_D1_PT_0 : STD_LOGIC; 
  signal err_n0020_MC_D1 : STD_LOGIC; 
  signal upper_dec_k_dec : STD_LOGIC; 
  signal err_n0020_MC_D2_PT_0 : STD_LOGIC; 
  signal err_n0020_MC_D2 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_Q : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D1 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_dec_k_dec_MC_D2 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_Q : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D1 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D2_PT_7 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D2_PT_8 : STD_LOGIC; 
  signal upper_dec_k_dec_MC_D2 : STD_LOGIC; 
  signal error_u_MC_Q : STD_LOGIC; 
  signal error_u_MC_D : STD_LOGIC; 
  signal error_u_MC_D1 : STD_LOGIC; 
  signal error_u_MC_D2_PT_0 : STD_LOGIC; 
  signal error_u_MC_D2_PT_1 : STD_LOGIC; 
  signal error_u_MC_D2_PT_2 : STD_LOGIC; 
  signal error_u_MC_D2_PT_3 : STD_LOGIC; 
  signal error_u_MC_D2_PT_4 : STD_LOGIC; 
  signal error_u_MC_D2_PT_5 : STD_LOGIC; 
  signal error_u_MC_D2_PT_6 : STD_LOGIC; 
  signal error_u_MC_D2_PT_7 : STD_LOGIC; 
  signal error_u_MC_D2_PT_8 : STD_LOGIC; 
  signal error_u_MC_D2_PT_9 : STD_LOGIC; 
  signal error_u_MC_D2_PT_10 : STD_LOGIC; 
  signal error_u_MC_D2_PT_11 : STD_LOGIC; 
  signal error_u_MC_D2_PT_12 : STD_LOGIC; 
  signal error_u_MC_D2_PT_13 : STD_LOGIC; 
  signal error_u_MC_D2_PT_14 : STD_LOGIC; 
  signal error_u_MC_D2_PT_15 : STD_LOGIC; 
  signal error_u_MC_D2_PT_16 : STD_LOGIC; 
  signal error_u_MC_D2_PT_17 : STD_LOGIC; 
  signal error_u_MC_D2_PT_18 : STD_LOGIC; 
  signal error_u_MC_D2_PT_19 : STD_LOGIC; 
  signal error_u_MC_D2 : STD_LOGIC; 
  signal err_ill_char_det5_MC_Q : STD_LOGIC; 
  signal err_ill_char_det5_MC_D : STD_LOGIC; 
  signal err_ill_char_det5_MC_D1 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_0 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_1 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_2 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_3 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_4 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_5 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_6 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_7 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_8 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_9 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_10 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_11 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_12 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_13 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_14 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2_PT_15 : STD_LOGIC; 
  signal err_ill_char_det5_MC_D2 : STD_LOGIC; 
  signal N_PZ_217_MC_Q : STD_LOGIC; 
  signal N_PZ_217_MC_D : STD_LOGIC; 
  signal N_PZ_217_MC_D1 : STD_LOGIC; 
  signal N_PZ_217_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_217_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_217_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_217_MC_D2 : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_prs_state_fft2_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_prs_state_fft2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_prs_state_fft1_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_prs_state_fft1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_prs_state_fft1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dec_8b10b_prs_state_ffd1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dec_8b10b_prs_state_ffd1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dec_8b10b_prs_state_ffd1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_dec_8b10b_prs_state_ffd2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_prs_state_ffd1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_prs_state_ffd1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_prs_state_ffd1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_err_chk_prs_state_ffd2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_5_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_5_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_6_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_7_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_7_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_7_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_8_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_8_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_lower_dec_hout_MC_D2_PT_8_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_188_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_188_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_309_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_309_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_prs_state_fft2_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_prs_state_fft2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_prs_state_fft1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_prs_state_fft1_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_prs_state_fft1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dec_8b10b_prs_state_ffd1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dec_8b10b_prs_state_ffd1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dec_8b10b_prs_state_ffd1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dec_8b10b_prs_state_ffd2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_err_chk_prs_state_ffd1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_err_chk_prs_state_ffd1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_err_chk_prs_state_ffd1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_err_chk_prs_state_ffd2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_hin_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_jin_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_fin_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_189_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_189_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_iin_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_ein_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_305_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_305_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_din_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cin_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_gin_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_7_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_9_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_9_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_eout_MC_D2_PT_9_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_298_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_298_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bin_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_308_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_308_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_ain_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_343_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_343_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_348_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_348_MC_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_348_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_348_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_dout_MC_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_7_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_cout_MC_D2_PT_8_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_7_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_dec_bout_MC_D2_PT_7_IN7 : STD_LOGIC;