testram.cr.mti

VERILOG HDL 实际工控项目源码

D:/altera/quartus41/eda/sim_lib/flex10ke_atoms.v {1 {vlog -work work D:/altera/quartus41/eda/sim_lib/flex10ke_atoms.v
Model Technology ModelSim SE vlog 5.8c Compiler 2004.03 Mar 25 2004
-- Compiling module flex10ke_asynch_lcell
-- Compiling module flex10ke_lcell_register
-- Compiling module flex10ke_lcell
-- Compiling module flex10ke_io
-- Compiling module flex10ke_asynch_io
-- Compiling module flex10ke_asynch_mem
-- Compiling UDP PRIM_DFFE
-- Compiling module dffe
-- Compiling module dffe_io
-- Compiling module mux21
-- Compiling module and1
-- Compiling module and11
-- Compiling module nmux21
-- Compiling module bmux21
-- Compiling module b5mux21
-- Compiling module flex10ke_ram_slice
-- Compiling module flex10ke_pll

Top level modules:
	flex10ke_lcell
	flex10ke_io
	and11
	b5mux21
	flex10ke_ram_slice
	flex10ke_pll

} {} {}} D:/altera/FPGApro/simulation/modelsim/testmyfifo.v {1 {vlog -work work D:/altera/FPGApro/simulation/modelsim/testmyfifo.v
Model Technology ModelSim SE vlog 5.8c Compiler 2004.03 Mar 25 2004
-- Compiling module myfifo
-- Compiling module t

Top level modules:
	t

} {} {}}