ad_collect.v

VERILOG HDL 实际工控项目源码

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// Generated by Quartus II Version 4.1 (Build Build 207 08/26/2004)
// Created on Mon Sep 06 10:14:40 2004

//  Module Declaration
`timescale 1ns/1ns
module ad_collect
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	rst, g_clk, ad_busy, ad_eoc, full_int, ad_cs, ad_sel, ad_rd, ad_wr, 
	ad_sl, ad_conv, wr_addr
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input rst;
	input g_clk;
	input ad_busy;
	input ad_eoc;
	output full_int;
	output ad_cs;
	output ad_sel;
	output ad_rd;
	output ad_wr;
	output [3:0] ad_sl;
	output ad_conv;
	output [2:0] wr_addr;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

reg ad_cs,ad_rd,ad_conv,full_int,ad_sel,ad_wr;
reg [11:0] delay;
reg [3:0] step;
reg [1:0] eoc_reg;
reg [3:0] ad_sl;
reg [2:0] wr_addr;

reg change_end ;
reg dir_4052;
reg [1:0] counter;

always @(posedge rst or posedge g_clk)
begin
	if(rst)
	eoc_reg<=0;
	else begin
		eoc_reg<={eoc_reg[0],ad_eoc};
		end
end

reg [1:0] collect_reg;
always @(posedge rst or posedge g_clk)
begin
	if(rst)
	collect_reg<=2'b00;
	else begin
		collect_reg<={collect_reg[0],full_int};
		end
end

always @(posedge rst or posedge g_clk)
begin
if(rst)
	begin
	ad_sel<=0;
	ad_sl<=4'b1111;
	ad_wr<=1;
	
	ad_rd<=1;
	ad_cs<=1;
	wr_addr<=0;
	step<=4'h0;
	ad_conv<=1;
	
	change_end<=0;
	counter<=0;
	delay<=0;
	end
else begin

	case (step) 
	 4'h0: begin
			if(collect_reg==2'b01)
			step<=4'h1;
		   end
	
     4'h1: begin
			ad_conv<=0;
			step<=4'h2;
		  	end					
	 4'h2: begin
			delay<=0;
			ad_conv<=1;
			step<=4'h3;
		   end
		  		 
	 4'h3: begin
			if(eoc_reg==2'b10)   //
				begin
					if(counter==0)
					dir_4052<=~dir_4052;//采完一路就切4052，因为是4中同步采样
					delay<=0;
					ad_cs<=0;
					step<=4'h4;
				end
			else 
				begin
					if(delay>=100)
					begin
						delay<=0;
						counter<=0;
						wr_addr<=0;
						step<=1;
					end
					else delay<=delay+1;
				end			
			 end
					
	  4'h4: begin
				ad_rd<=0;
				step<=4'h5;
			end		
	  
	  4'h5: begin
	  			ad_rd<=1;
				step<=4'h6;
			end		
				
	  4'h6: begin
	  			ad_cs<=1;
				step<=4'h7;  
			end	

	  4'h7: begin
				wr_addr<=wr_addr+1;		
			  	if(counter==2'b11)//每次采４个
				   begin
				  	counter<=0;
					change_end<=~change_end;
					step<=4'h8;
				   end
			   	 else begin
						counter<=counter+1;
					 	step<=4'h3;
				      end
				  
		       end
		       
	   4'h8: begin
		 		if(change_end==0)
		 			step<=4'h0;
		 		else step<=4'h1;
		 	 end
	  
		default: step<=4'h0;
		endcase	
	 end
end	

reg [10:0] int_reg;
	
always @(posedge rst or posedge g_clk)
if(rst)
	begin
		int_reg<=0;
		full_int<=1;
	end
else begin 
		int_reg<=int_reg+1;	
		if(int_reg<1800)
		begin
			full_int<=1;
		end
	 	else if((int_reg>=1800)&&(int_reg<1830))
			begin
			full_int<=0;
			end	
		else if(int_reg>=1830)
			  begin
				int_reg<=0;
		      end
	end

endmodule