myfifo.fit.eqn

VERILOG HDL 实际工控项目源码

D1L21 = D1L11 & (D1_coll_mem[7][11] # !rd_addr[0]) # !D1L11 & rd_addr[0] & D1_coll_mem[5][11];


--D1_coll_mem[2][11] is mydram:inst2|coll_mem[2][11] at LC4_B24
--operation mode is normal

D1_coll_mem[2][11]_lut_out = ad_db[11];
D1_coll_mem[2][11] = DFFEA(D1_coll_mem[2][11]_lut_out, GLOBAL(g_clk), , , D1L231, , );


--D1_coll_mem[1][11] is mydram:inst2|coll_mem[1][11] at LC5_B24
--operation mode is normal

D1_coll_mem[1][11]_lut_out = ad_db[11];
D1_coll_mem[1][11] = DFFEA(D1_coll_mem[1][11]_lut_out, GLOBAL(g_clk), , , D1L611, , );


--D1_coll_mem[0][11] is mydram:inst2|coll_mem[0][11] at LC6_B24
--operation mode is normal

D1_coll_mem[0][11]_lut_out = ad_db[11];
D1_coll_mem[0][11] = DFFEA(D1_coll_mem[0][11]_lut_out, GLOBAL(g_clk), , , D1L001, , );


--D1L9 is mydram:inst2|Mux~300 at LC7_B24
--operation mode is normal

D1L9 = rd_addr[0] & (D1_coll_mem[1][11] # rd_addr[1]) # !rd_addr[0] & D1_coll_mem[0][11] & !rd_addr[1];


--D1_coll_mem[3][11] is mydram:inst2|coll_mem[3][11] at LC8_B24
--operation mode is normal

D1_coll_mem[3][11]_lut_out = ad_db[11];
D1_coll_mem[3][11] = DFFEA(D1_coll_mem[3][11]_lut_out, GLOBAL(g_clk), , , D1L841, , );


--D1L01 is mydram:inst2|Mux~301 at LC1_B24
--operation mode is normal

D1L01 = D1L9 & (D1_coll_mem[3][11] # !rd_addr[1]) # !D1L9 & rd_addr[1] & D1_coll_mem[2][11];


--D1L16 is mydram:inst2|Mux~620 at LC3_B11
--operation mode is normal

D1L16 = !rd_addr[3] & (rd_addr[2] & D1L21 # !rd_addr[2] & D1L01);


--D1_coll_mem[8][11] is mydram:inst2|coll_mem[8][11] at LC7_B11
--operation mode is normal

D1_coll_mem[8][11]_lut_out = D1_rdy_reg[11];
D1_coll_mem[8][11] = DFFEA(D1_coll_mem[8][11]_lut_out, GLOBAL(g_clk), , , , , );


--D1L26 is mydram:inst2|Mux~621 at LC8_B11
--operation mode is normal

D1L26 = D1L16 # D1_coll_mem[8][11] & rd_addr[3];


--D1L262 is mydram:inst2|d_out[11]~2424 at LC6_B11
--operation mode is normal

D1L262 = (rd_add[14] # E1_dsp_flash_oe # !D1L372 # !D1L26) & CASCADE(D1L362);


--D1_coll_mem[5][10] is mydram:inst2|coll_mem[5][10] at LC1_D13
--operation mode is normal

D1_coll_mem[5][10]_lut_out = ad_db[10];
D1_coll_mem[5][10] = DFFEA(D1_coll_mem[5][10]_lut_out, GLOBAL(g_clk), , , D1L081, , );


--D1_coll_mem[6][10] is mydram:inst2|coll_mem[6][10] at LC3_D13
--operation mode is normal

D1_coll_mem[6][10]_lut_out = ad_db[10];
D1_coll_mem[6][10] = DFFEA(D1_coll_mem[6][10]_lut_out, GLOBAL(g_clk), , , D1L691, , );


--D1_coll_mem[4][10] is mydram:inst2|coll_mem[4][10] at LC4_D13
--operation mode is normal

D1_coll_mem[4][10]_lut_out = ad_db[10];
D1_coll_mem[4][10] = DFFEA(D1_coll_mem[4][10]_lut_out, GLOBAL(g_clk), , , D1L461, , );


--D1L51 is mydram:inst2|Mux~306 at LC5_D13
--operation mode is normal

D1L51 = rd_addr[1] & (D1_coll_mem[6][10] # rd_addr[0]) # !rd_addr[1] & D1_coll_mem[4][10] & !rd_addr[0];


--D1_coll_mem[7][10] is mydram:inst2|coll_mem[7][10] at LC6_D13
--operation mode is normal

D1_coll_mem[7][10]_lut_out = ad_db[10];
D1_coll_mem[7][10] = DFFEA(D1_coll_mem[7][10]_lut_out, GLOBAL(g_clk), , , D1L212, , );


--D1L61 is mydram:inst2|Mux~307 at LC7_D13
--operation mode is normal

D1L61 = D1L51 & (D1_coll_mem[7][10] # !rd_addr[0]) # !D1L51 & rd_addr[0] & D1_coll_mem[5][10];


--D1_coll_mem[2][10] is mydram:inst2|coll_mem[2][10] at LC3_D23
--operation mode is normal

D1_coll_mem[2][10]_lut_out = ad_db[10];
D1_coll_mem[2][10] = DFFEA(D1_coll_mem[2][10]_lut_out, GLOBAL(g_clk), , , D1L231, , );


--D1_coll_mem[1][10] is mydram:inst2|coll_mem[1][10] at LC2_D13
--operation mode is normal

D1_coll_mem[1][10]_lut_out = ad_db[10];
D1_coll_mem[1][10] = DFFEA(D1_coll_mem[1][10]_lut_out, GLOBAL(g_clk), , , D1L611, , );


--D1_coll_mem[0][10] is mydram:inst2|coll_mem[0][10] at LC4_D23
--operation mode is normal

D1_coll_mem[0][10]_lut_out = ad_db[10];
D1_coll_mem[0][10] = DFFEA(D1_coll_mem[0][10]_lut_out, GLOBAL(g_clk), , , D1L001, , );


--D1L31 is mydram:inst2|Mux~304 at LC5_D23
--operation mode is normal

D1L31 = rd_addr[0] & (D1_coll_mem[1][10] # rd_addr[1]) # !rd_addr[0] & D1_coll_mem[0][10] & !rd_addr[1];


--D1_coll_mem[3][10] is mydram:inst2|coll_mem[3][10] at LC6_D23
--operation mode is normal

D1_coll_mem[3][10]_lut_out = ad_db[10];
D1_coll_mem[3][10] = DFFEA(D1_coll_mem[3][10]_lut_out, GLOBAL(g_clk), , , D1L841, , );


--D1L41 is mydram:inst2|Mux~305 at LC2_D23
--operation mode is normal

D1L41 = D1L31 & (D1_coll_mem[3][10] # !rd_addr[1]) # !D1L31 & rd_addr[1] & D1_coll_mem[2][10];


--D1L36 is mydram:inst2|Mux~622 at LC8_D13
--operation mode is normal

D1L36 = !rd_addr[3] & (rd_addr[2] & D1L61 # !rd_addr[2] & D1L41);


--D1_coll_mem[8][10] is mydram:inst2|coll_mem[8][10] at LC2_B3
--operation mode is normal

D1_coll_mem[8][10]_lut_out = D1_rdy_reg[10];
D1_coll_mem[8][10] = DFFEA(D1_coll_mem[8][10]_lut_out, GLOBAL(g_clk), , , , , );


--D1L46 is mydram:inst2|Mux~623 at LC8_B4
--operation mode is normal

D1L46 = D1L36 # D1_coll_mem[8][10] & rd_addr[3];


--D1L952 is mydram:inst2|d_out[10]~2425 at LC7_B4
--operation mode is normal

D1L952 = (rd_add[14] # E1_dsp_flash_oe # !D1L372 # !D1L46) & CASCADE(D1L062);


--D1_coll_mem[5][9] is mydram:inst2|coll_mem[5][9] at LC3_D15
--operation mode is normal

D1_coll_mem[5][9]_lut_out = ad_db[9];
D1_coll_mem[5][9] = DFFEA(D1_coll_mem[5][9]_lut_out, GLOBAL(g_clk), , , D1L081, , );


--D1_coll_mem[6][9] is mydram:inst2|coll_mem[6][9] at LC4_D15
--operation mode is normal

D1_coll_mem[6][9]_lut_out = ad_db[9];
D1_coll_mem[6][9] = DFFEA(D1_coll_mem[6][9]_lut_out, GLOBAL(g_clk), , , D1L691, , );


--D1_coll_mem[4][9] is mydram:inst2|coll_mem[4][9] at LC5_D15
--operation mode is normal

D1_coll_mem[4][9]_lut_out = ad_db[9];
D1_coll_mem[4][9] = DFFEA(D1_coll_mem[4][9]_lut_out, GLOBAL(g_clk), , , D1L461, , );


--D1L91 is mydram:inst2|Mux~310 at LC6_D15
--operation mode is normal

D1L91 = rd_addr[1] & (D1_coll_mem[6][9] # rd_addr[0]) # !rd_addr[1] & D1_coll_mem[4][9] & !rd_addr[0];


--D1_coll_mem[7][9] is mydram:inst2|coll_mem[7][9] at LC7_D15
--operation mode is normal

D1_coll_mem[7][9]_lut_out = ad_db[9];
D1_coll_mem[7][9] = DFFEA(D1_coll_mem[7][9]_lut_out, GLOBAL(g_clk), , , D1L212, , );


--D1L02 is mydram:inst2|Mux~311 at LC8_D15
--operation mode is normal

D1L02 = D1L91 & (D1_coll_mem[7][9] # !rd_addr[0]) # !D1L91 & rd_addr[0] & D1_coll_mem[5][9];


--D1_coll_mem[2][9] is mydram:inst2|coll_mem[2][9] at LC7_D23
--operation mode is normal

D1_coll_mem[2][9]_lut_out = ad_db[9];
D1_coll_mem[2][9] = DFFEA(D1_coll_mem[2][9]_lut_out, GLOBAL(g_clk), , , D1L231, , );


--D1_coll_mem[1][9] is mydram:inst2|coll_mem[1][9] at LC3_D19
--operation mode is normal

D1_coll_mem[1][9]_lut_out = ad_db[9];
D1_coll_mem[1][9] = DFFEA(D1_coll_mem[1][9]_lut_out, GLOBAL(g_clk), , , D1L611, , );


--D1_coll_mem[0][9] is mydram:inst2|coll_mem[0][9] at LC2_D15
--operation mode is normal

D1_coll_mem[0][9]_lut_out = ad_db[9];
D1_coll_mem[0][9] = DFFEA(D1_coll_mem[0][9]_lut_out, GLOBAL(g_clk), , , D1L001, , );


--D1L71 is mydram:inst2|Mux~308 at LC1_D19
--operation mode is normal

D1L71 = rd_addr[0] & (D1_coll_mem[1][9] # rd_addr[1]) # !rd_addr[0] & D1_coll_mem[0][9] & !rd_addr[1];


--D1_coll_mem[3][9] is mydram:inst2|coll_mem[3][9] at LC8_D23
--operation mode is normal

D1_coll_mem[3][9]_lut_out = ad_db[9];
D1_coll_mem[3][9] = DFFEA(D1_coll_mem[3][9]_lut_out, GLOBAL(g_clk), , , D1L841, , );


--D1L81 is mydram:inst2|Mux~309 at LC1_D23
--operation mode is normal

D1L81 = D1L71 & (D1_coll_mem[3][9] # !rd_addr[1]) # !D1L71 & rd_addr[1] & D1_coll_mem[2][9];


--D1L56 is mydram:inst2|Mux~624 at LC1_D15
--operation mode is normal

D1L56 = !rd_addr[3] & (rd_addr[2] & D1L02 # !rd_addr[2] & D1L81);


--D1_coll_mem[8][9] is mydram:inst2|coll_mem[8][9] at LC5_B3
--operation mode is normal

D1_coll_mem[8][9]_lut_out = D1_rdy_reg[9];
D1_coll_mem[8][9] = DFFEA(D1_coll_mem[8][9]_lut_out, GLOBAL(g_clk), , , , , );


--D1L66 is mydram:inst2|Mux~625 at LC1_D7
--operation mode is normal

D1L66 = D1L56 # D1_coll_mem[8][9] & rd_addr[3];


--D1L652 is mydram:inst2|d_out[9]~2426 at LC4_D7
--operation mode is normal

D1L652 = (rd_add[14] # E1_dsp_flash_oe # !D1L372 # !D1L66) & CASCADE(D1L752);


--D1_coll_mem[5][8] is mydram:inst2|coll_mem[5][8] at LC3_B14
--operation mode is normal

D1_coll_mem[5][8]_lut_out = ad_db[8];
D1_coll_mem[5][8] = DFFEA(D1_coll_mem[5][8]_lut_out, GLOBAL(g_clk), , , D1L081, , );


--D1_coll_mem[6][8] is mydram:inst2|coll_mem[6][8] at LC1_B18
--operation mode is normal

D1_coll_mem[6][8]_lut_out = ad_db[8];
D1_coll_mem[6][8] = DFFEA(D1_coll_mem[6][8]_lut_out, GLOBAL(g_clk), , , D1L691, , );


--D1_coll_mem[4][8] is mydram:inst2|coll_mem[4][8] at LC3_B18
--operation mode is normal

D1_coll_mem[4][8]_lut_out = ad_db[8];
D1_coll_mem[4][8] = DFFEA(D1_coll_mem[4][8]_lut_out, GLOBAL(g_clk), , , D1L461, , );


--D1L32 is mydram:inst2|Mux~314 at LC2_B18
--operation mode is normal

D1L32 = rd_addr[1] & (D1_coll_mem[6][8] # rd_addr[0]) # !rd_addr[1] & D1_coll_mem[4][8] & !rd_addr[0];


--D1_coll_mem[7][8] is mydram:inst2|coll_mem[7][8] at LC4_B14
--operation mode is normal

D1_coll_mem[7][8]_lut_out = ad_db[8];
D1_coll_mem[7][8] = DFFEA(D1_coll_mem[7][8]_lut_out, GLOBAL(g_clk), , , D1L212, , );


--D1L42 is mydram:inst2|Mux~315 at LC2_B14
--operation mode is normal

D1L42 = D1L32 & (D1_coll_mem[7][8] # !rd_addr[0]) # !D1L32 & rd_addr[0] & D1_coll_mem[5][8];


--D1_coll_mem[2][8] is mydram:inst2|coll_mem[2][8] at LC4_D19
--operation mode is normal

D1_coll_mem[2][8]_lut_out = ad_db[8];
D1_coll_mem[2][8] = DFFEA(D1_coll_mem[2][8]_lut_out, GLOBAL(g_clk), , , D1L231, , );


--D1_coll_mem[1][8] is mydram:inst2|coll_mem[1][8] at LC5_D19
--operation mode is normal

D1_coll_mem[1][8]_lut_out = ad_db[8];
D1_coll_mem[1][8] = DFFEA(D1_coll_mem[1][8]_lut_out, GLOBAL(g_clk), , , D1L611, , );


--D1_coll_mem[0][8] is mydram:inst2|coll_mem[0][8] at LC6_D19
--operation mode is normal

D1_coll_mem[0][8]_lut_out = ad_db[8];
D1_coll_mem[0][8] = DFFEA(D1_coll_mem[0][8]_lut_out, GLOBAL(g_clk), , , D1L001, , );


--D1L12 is mydram:inst2|Mux~312 at LC7_D19
--operation mode is normal

D1L12 = rd_addr[0] & (D1_coll_mem[1][8] # rd_addr[1]) # !rd_addr[0] & D1_coll_mem[0][8] & !rd_addr[1];


--D1_coll_mem[3][8] is mydram:inst2|coll_mem[3][8] at LC8_D19
--operation mode is normal

D1_coll_mem[3][8]_lut_out = ad_db[8];
D1_coll_mem[3][8] = DFFEA(D1_coll_mem[3][8]_lut_out, GLOBAL(g_clk), , , D1L841, , );


--D1L22 is mydram:inst2|Mux~313 at LC2_D19
--operation mode is normal

D1L22 = D1L12 & (D1_coll_mem[3][8] # !rd_addr[1]) # !D1L12 & rd_addr[1] & D1_coll_mem[2][8];


--D1L76 is mydram:inst2|Mux~626 at LC6_B12
--operation mode is normal

D1L76 = !rd_addr[3] & (rd_addr[2] & D1L42 # !rd_addr[2] & D1L22);


--D1_coll_mem[8][8] is mydram:inst2|coll_mem[8][8] at LC7_B12
--operation mode is normal

D1_coll_mem[8][8]_lut_out = D1_rdy_reg[8];
D1_coll_mem[8][8] = DFFEA(D1_coll_mem[8][8]_lut_out, GLOBAL(g_clk), , , , , );


--D1L86 is mydram:inst2|Mux~627 at LC8_B12
--operation mode is normal

D1L86 = D1L76 # D1_coll_mem[8][8] & rd_addr[3];


--D1L352 is mydram:inst2|d_out[8]~2427 at LC5_B12
--operation mode is normal

D1L352 = (rd_add[14] # E1_dsp_flash_oe # !D1L372 # !D1L86) & CASCADE(D1L452);


--D1_coll_mem[5][7] is mydram:inst2|coll_mem[5][7] at LC4_B15
--operation mode is normal

D1_coll_mem[5][7]_lut_out = ad_db[7];
D1_coll_mem[5][7] = DFFEA(D1_coll_mem[5][7]_lut_out, GLOBAL(g_clk), , , D1L081, , );


--D1_coll_mem[6][7] is mydram:inst2|coll_mem[6][7] at LC4_B18
--operation mode is normal

D1_coll_mem[6][7]_lut_out = ad_db[7];
D1_coll_mem[6][7] = DFFEA(D1_coll_mem[6][7]_lut_out, GLOBAL(g_clk), , , D1L691, , );


--D1_coll_mem[4][7] is mydram:inst2|coll_mem[4][7] at LC5_B18
--operation mode is normal

D1_coll_mem[4][7]_lut_out = ad_db[7];
D1_coll_mem[4][7] = DFFEA(D1_coll_mem[4][7]_lut_out, GLOBAL(g_clk), , , D1L461, , );


--D1L72 is mydram:inst2|Mux~318 at LC6_B18
--operation mode is normal

D1L72 = rd_addr[1] & (D1_coll_mem[6][7] # rd_addr[0]) # !rd_addr[1] & D1_coll_mem[4][7] & !rd_addr[0];


--D1_coll_mem[7][7] is mydram:inst2|coll_mem[7][7] at LC7_B18
--operation mode is normal

D1_coll_mem[7][7]_lut_out = ad_db[7];
D1_coll_mem[7][7] = DFFEA(D1_coll_mem[7][7]_lut_out, GLOBAL(g_clk), , , D1L212, , );


--D1L82 is mydram:inst2|Mux~319 at LC8_B18
--operation mode is normal

D1L82 = D1L72 & (D1_coll_mem[7][7] # !rd_addr[0]) # !D1L72 & rd_addr[0] & D1_coll_mem[5][7];


--D1_c