myfifo.fit.eqn

VERILOG HDL 实际工控项目源码

J6_cout[5] = CARRY(C1_delay[5] & J6_cout[4]);


--J6_cs_buffer[6] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC1_F15
--operation mode is arithmetic

J6_cs_buffer[6] = C1_delay[6] $ J6_cout[5];

--J6_cout[6] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[6] at LC1_F15
--operation mode is arithmetic

J6_cout[6] = CARRY(C1_delay[6] & J6_cout[5]);


--J6_cs_buffer[4] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC7_F13
--operation mode is arithmetic

J6_cs_buffer[4] = C1_delay[4] $ J6_cout[3];

--J6_cout[4] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4] at LC7_F13
--operation mode is arithmetic

J6_cout[4] = CARRY(C1_delay[4] & J6_cout[3]);


--J6_cs_buffer[3] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC6_F13
--operation mode is arithmetic

J6_cs_buffer[3] = C1_delay[3] $ J6_cout[2];

--J6_cout[3] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3] at LC6_F13
--operation mode is arithmetic

J6_cout[3] = CARRY(C1_delay[3] & J6_cout[2]);


--J6_cs_buffer[2] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC5_F13
--operation mode is arithmetic

J6_cs_buffer[2] = C1_delay[2] $ J6_cout[1];

--J6_cout[2] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] at LC5_F13
--operation mode is arithmetic

J6_cout[2] = CARRY(C1_delay[2] & J6_cout[1]);


--C1L7 is ad_collect:inst1|Select~126 at LC6_F21
--operation mode is normal

C1L7 = C1L95Q & (C1_counter[0] $ C1_counter[1]);


--C1L61 is ad_collect:inst1|Select~2340 at LC8_F16
--operation mode is normal

C1L61 = C1L36Q & (!C1_eoc_reg[0] & C1_eoc_reg[1] # !C1L5);


--C1L45 is ad_collect:inst1|reduce_or~11 at LC1_F3
--operation mode is normal

C1L45 = C1L56Q # C1L46Q # C1L06Q # !C1L55;


--D1_rdy_reg[8] is mydram:inst2|rdy_reg[8] at LC1_B10
--operation mode is normal

D1_rdy_reg[8]_lut_out = A1L67;
D1_rdy_reg[8] = DFFEA(D1_rdy_reg[8]_lut_out, D1_rdy_en, , , , , );


--D1_rdy_reg[7] is mydram:inst2|rdy_reg[7] at LC4_C4
--operation mode is normal

D1_rdy_reg[7]_lut_out = A1L77;
D1_rdy_reg[7] = DFFEA(D1_rdy_reg[7]_lut_out, D1_rdy_en, , , , , );


--D1_rdy_reg[9] is mydram:inst2|rdy_reg[9] at LC3_B3
--operation mode is normal

D1_rdy_reg[9]_lut_out = A1L57;
D1_rdy_reg[9] = DFFEA(D1_rdy_reg[9]_lut_out, D1_rdy_en, , , , , );


--D1_rdy_reg[6] is mydram:inst2|rdy_reg[6] at LC4_C2
--operation mode is normal

D1_rdy_reg[6]_lut_out = A1L87;
D1_rdy_reg[6] = DFFEA(D1_rdy_reg[6]_lut_out, D1_rdy_en, , , , , );


--D1L392 is mydram:inst2|reduce_nor~99 at LC7_B3
--operation mode is normal

D1L392 = !D1_rdy_reg[6] & !D1_rdy_reg[9] & D1_rdy_reg[7] & D1_rdy_reg[8];


--D1_rdy_reg[13] is mydram:inst2|rdy_reg[13] at LC1_B1
--operation mode is normal

D1_rdy_reg[13]_lut_out = A1L17;
D1_rdy_reg[13] = DFFEA(D1_rdy_reg[13]_lut_out, D1_rdy_en, , , , , );


--D1_rdy_reg[10] is mydram:inst2|rdy_reg[10] at LC4_B3
--operation mode is normal

D1_rdy_reg[10]_lut_out = A1L47;
D1_rdy_reg[10] = DFFEA(D1_rdy_reg[10]_lut_out, D1_rdy_en, , , , , );


--D1_rdy_reg[12] is mydram:inst2|rdy_reg[12] at LC2_B7
--operation mode is normal

D1_rdy_reg[12]_lut_out = A1L27;
D1_rdy_reg[12] = DFFEA(D1_rdy_reg[12]_lut_out, D1_rdy_en, , , , , );


--D1_rdy_reg[11] is mydram:inst2|rdy_reg[11] at LC1_B3
--operation mode is normal

D1_rdy_reg[11]_lut_out = A1L37;
D1_rdy_reg[11] = DFFEA(D1_rdy_reg[11]_lut_out, D1_rdy_en, , , , , );


--D1L492 is mydram:inst2|reduce_nor~101 at LC8_B3
--operation mode is normal

D1L492 = (!D1_rdy_reg[11] & !D1_rdy_reg[12] & D1_rdy_reg[10] & D1_rdy_reg[13]) & CASCADE(D1L392);


--G1_unreg_res_node[25] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[25] at LC5_E23
--operation mode is normal

G1_unreg_res_node[25] = J3_cout[24] $ B1_watch_reg[25];


--G2_unreg_res_node[11] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[11] at LC6_F15
--operation mode is normal

G2_unreg_res_node[11] = J6_cout[10] $ C1_delay[11];


--C1L71 is ad_collect:inst1|Select~2343 at LC2_F16
--operation mode is normal

C1L71 = C1_change_end & !C1L75Q & (C1L85Q # !C1L51) # !C1_change_end & (C1L85Q # !C1L51);


--C1L81 is ad_collect:inst1|Select~2345 at LC3_F16
--operation mode is normal

C1L81 = (!C1_eoc_reg[0] & C1_eoc_reg[1] # !C1L36Q # !C1L5) & CASCADE(C1L71);


--J3_cs_buffer[5] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC1_E19
--operation mode is arithmetic

J3_cs_buffer[5] = B1_watch_reg[5] $ J3_cout[4];

--J3_cout[5] is watchdog:inst|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] at LC1_E19
--operation mode is arithmetic

J3_cout[5] = CARRY(B1_watch_reg[5] & J3_cout[4]);


--J6_cs_buffer[1] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC4_F13
--operation mode is arithmetic

J6_cs_buffer[1] = C1_delay[1] $ J6_cout[0];

--J6_cout[1] is ad_collect:inst1|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[1] at LC4_F13
--operation mode is arithmetic

J6_cout[1] = CARRY(C1_delay[1] & J6_cout[0]);


--D1_coll_mem[5][13] is mydram:inst2|coll_mem[5][13] at LC3_B17
--operation mode is normal

D1_coll_mem[5][13]_lut_out = !ad_db[13];
D1_coll_mem[5][13] = DFFEA(D1_coll_mem[5][13]_lut_out, GLOBAL(g_clk), , , D1L081, , );


--D1_coll_mem[6][13] is mydram:inst2|coll_mem[6][13] at LC4_B17
--operation mode is normal

D1_coll_mem[6][13]_lut_out = !ad_db[13];
D1_coll_mem[6][13] = DFFEA(D1_coll_mem[6][13]_lut_out, GLOBAL(g_clk), , , D1L691, , );


--D1_coll_mem[4][13] is mydram:inst2|coll_mem[4][13] at LC5_B17
--operation mode is normal

D1_coll_mem[4][13]_lut_out = !ad_db[13];
D1_coll_mem[4][13] = DFFEA(D1_coll_mem[4][13]_lut_out, GLOBAL(g_clk), , , D1L461, , );


--D1L3 is mydram:inst2|Mux~294 at LC6_B17
--operation mode is normal

D1L3 = rd_addr[1] & (D1_coll_mem[6][13] # rd_addr[0]) # !rd_addr[1] & D1_coll_mem[4][13] & !rd_addr[0];


--D1_coll_mem[7][13] is mydram:inst2|coll_mem[7][13] at LC7_B17
--operation mode is normal

D1_coll_mem[7][13]_lut_out = !ad_db[13];
D1_coll_mem[7][13] = DFFEA(D1_coll_mem[7][13]_lut_out, GLOBAL(g_clk), , , D1L212, , );


--D1L4 is mydram:inst2|Mux~295 at LC2_B17
--operation mode is normal

D1L4 = D1L3 & (D1_coll_mem[7][13] # !rd_addr[0]) # !D1L3 & rd_addr[0] & D1_coll_mem[5][13];


--D1_coll_mem[2][13] is mydram:inst2|coll_mem[2][13] at LC3_B23
--operation mode is normal

D1_coll_mem[2][13]_lut_out = !ad_db[13];
D1_coll_mem[2][13] = DFFEA(D1_coll_mem[2][13]_lut_out, GLOBAL(g_clk), , , D1L231, , );


--D1_coll_mem[1][13] is mydram:inst2|coll_mem[1][13] at LC4_B23
--operation mode is normal

D1_coll_mem[1][13]_lut_out = !ad_db[13];
D1_coll_mem[1][13] = DFFEA(D1_coll_mem[1][13]_lut_out, GLOBAL(g_clk), , , D1L611, , );


--D1_coll_mem[0][13] is mydram:inst2|coll_mem[0][13] at LC5_B23
--operation mode is normal

D1_coll_mem[0][13]_lut_out = !ad_db[13];
D1_coll_mem[0][13] = DFFEA(D1_coll_mem[0][13]_lut_out, GLOBAL(g_clk), , , D1L001, , );


--D1L1 is mydram:inst2|Mux~292 at LC6_B23
--operation mode is normal

D1L1 = rd_addr[0] & (D1_coll_mem[1][13] # rd_addr[1]) # !rd_addr[0] & D1_coll_mem[0][13] & !rd_addr[1];


--D1_coll_mem[3][13] is mydram:inst2|coll_mem[3][13] at LC1_B17
--operation mode is normal

D1_coll_mem[3][13]_lut_out = !ad_db[13];
D1_coll_mem[3][13] = DFFEA(D1_coll_mem[3][13]_lut_out, GLOBAL(g_clk), , , D1L841, , );


--D1L2 is mydram:inst2|Mux~293 at LC2_B23
--operation mode is normal

D1L2 = D1L1 & (D1_coll_mem[3][13] # !rd_addr[1]) # !D1L1 & rd_addr[1] & D1_coll_mem[2][13];


--D1L75 is mydram:inst2|Mux~616 at LC3_B10
--operation mode is normal

D1L75 = !rd_addr[3] & (rd_addr[2] & D1L4 # !rd_addr[2] & D1L2);


--D1_coll_mem[8][13] is mydram:inst2|coll_mem[8][13] at LC4_B10
--operation mode is normal

D1_coll_mem[8][13]_lut_out = D1_rdy_reg[13];
D1_coll_mem[8][13] = DFFEA(D1_coll_mem[8][13]_lut_out, GLOBAL(g_clk), , , , , );


--D1L85 is mydram:inst2|Mux~617 at LC2_B10
--operation mode is normal

D1L85 = D1L75 # D1_coll_mem[8][13] & rd_addr[3];


--D1L862 is mydram:inst2|d_out[13]~2422 at LC2_B12
--operation mode is normal

D1L862 = (rd_add[14] # E1_dsp_flash_oe # !D1L372 # !D1L85) & CASCADE(D1L962);


--D1_coll_mem[5][12] is mydram:inst2|coll_mem[5][12] at LC3_B22
--operation mode is normal

D1_coll_mem[5][12]_lut_out = ad_db[12];
D1_coll_mem[5][12] = DFFEA(D1_coll_mem[5][12]_lut_out, GLOBAL(g_clk), , , D1L081, , );


--D1_coll_mem[6][12] is mydram:inst2|coll_mem[6][12] at LC4_B22
--operation mode is normal

D1_coll_mem[6][12]_lut_out = ad_db[12];
D1_coll_mem[6][12] = DFFEA(D1_coll_mem[6][12]_lut_out, GLOBAL(g_clk), , , D1L691, , );


--D1_coll_mem[4][12] is mydram:inst2|coll_mem[4][12] at LC5_B22
--operation mode is normal

D1_coll_mem[4][12]_lut_out = ad_db[12];
D1_coll_mem[4][12] = DFFEA(D1_coll_mem[4][12]_lut_out, GLOBAL(g_clk), , , D1L461, , );


--D1L7 is mydram:inst2|Mux~298 at LC6_B22
--operation mode is normal

D1L7 = rd_addr[1] & (D1_coll_mem[6][12] # rd_addr[0]) # !rd_addr[1] & D1_coll_mem[4][12] & !rd_addr[0];


--D1_coll_mem[7][12] is mydram:inst2|coll_mem[7][12] at LC7_B22
--operation mode is normal

D1_coll_mem[7][12]_lut_out = ad_db[12];
D1_coll_mem[7][12] = DFFEA(D1_coll_mem[7][12]_lut_out, GLOBAL(g_clk), , , D1L212, , );


--D1L8 is mydram:inst2|Mux~299 at LC8_B22
--operation mode is normal

D1L8 = D1L7 & (D1_coll_mem[7][12] # !rd_addr[0]) # !D1L7 & rd_addr[0] & D1_coll_mem[5][12];


--D1_coll_mem[2][12] is mydram:inst2|coll_mem[2][12] at LC3_B24
--operation mode is normal

D1_coll_mem[2][12]_lut_out = ad_db[12];
D1_coll_mem[2][12] = DFFEA(D1_coll_mem[2][12]_lut_out, GLOBAL(g_clk), , , D1L231, , );


--D1_coll_mem[1][12] is mydram:inst2|coll_mem[1][12] at LC7_B23
--operation mode is normal

D1_coll_mem[1][12]_lut_out = ad_db[12];
D1_coll_mem[1][12] = DFFEA(D1_coll_mem[1][12]_lut_out, GLOBAL(g_clk), , , D1L611, , );


--D1_coll_mem[0][12] is mydram:inst2|coll_mem[0][12] at LC8_B23
--operation mode is normal

D1_coll_mem[0][12]_lut_out = ad_db[12];
D1_coll_mem[0][12] = DFFEA(D1_coll_mem[0][12]_lut_out, GLOBAL(g_clk), , , D1L001, , );


--D1L5 is mydram:inst2|Mux~296 at LC1_B23
--operation mode is normal

D1L5 = rd_addr[0] & (D1_coll_mem[1][12] # rd_addr[1]) # !rd_addr[0] & D1_coll_mem[0][12] & !rd_addr[1];


--D1_coll_mem[3][12] is mydram:inst2|coll_mem[3][12] at LC1_B22
--operation mode is normal

D1_coll_mem[3][12]_lut_out = ad_db[12];
D1_coll_mem[3][12] = DFFEA(D1_coll_mem[3][12]_lut_out, GLOBAL(g_clk), , , D1L841, , );


--D1L6 is mydram:inst2|Mux~297 at LC2_B24
--operation mode is normal

D1L6 = D1L5 & (D1_coll_mem[3][12] # !rd_addr[1]) # !D1L5 & rd_addr[1] & D1_coll_mem[2][12];


--D1L95 is mydram:inst2|Mux~618 at LC2_B22
--operation mode is normal

D1L95 = !rd_addr[3] & (rd_addr[2] & D1L8 # !rd_addr[2] & D1L6);


--D1_coll_mem[8][12] is mydram:inst2|coll_mem[8][12] at LC1_B7
--operation mode is normal

D1_coll_mem[8][12]_lut_out = D1_rdy_reg[12];
D1_coll_mem[8][12] = DFFEA(D1_coll_mem[8][12]_lut_out, GLOBAL(g_clk), , , , , );


--D1L06 is mydram:inst2|Mux~619 at LC1_B4
--operation mode is normal

D1L06 = D1L95 # D1_coll_mem[8][12] & rd_addr[3];


--D1L562 is mydram:inst2|d_out[12]~2423 at LC4_B4
--operation mode is normal

D1L562 = (rd_add[14] # E1_dsp_flash_oe # !D1L372 # !D1L06) & CASCADE(D1L662);


--D1_coll_mem[5][11] is mydram:inst2|coll_mem[5][11] at LC2_B6
--operation mode is normal

D1_coll_mem[5][11]_lut_out = ad_db[11];
D1_coll_mem[5][11] = DFFEA(D1_coll_mem[5][11]_lut_out, GLOBAL(g_clk), , , D1L081, , );


--D1_coll_mem[6][11] is mydram:inst2|coll_mem[6][11] at LC3_B6
--operation mode is normal

D1_coll_mem[6][11]_lut_out = ad_db[11];
D1_coll_mem[6][11] = DFFEA(D1_coll_mem[6][11]_lut_out, GLOBAL(g_clk), , , D1L691, , );


--D1_coll_mem[4][11] is mydram:inst2|coll_mem[4][11] at LC4_B6
--operation mode is normal

D1_coll_mem[4][11]_lut_out = ad_db[11];
D1_coll_mem[4][11] = DFFEA(D1_coll_mem[4][11]_lut_out, GLOBAL(g_clk), , , D1L461, , );


--D1L11 is mydram:inst2|Mux~302 at LC5_B6
--operation mode is normal

D1L11 = rd_addr[1] & (D1_coll_mem[6][11] # rd_addr[0]) # !rd_addr[1] & D1_coll_mem[4][11] & !rd_addr[0];


--D1_coll_mem[7][11] is mydram:inst2|coll_mem[7][11] at LC6_B6
--operation mode is normal

D1_coll_mem[7][11]_lut_out = ad_db[11];
D1_coll_mem[7][11] = DFFEA(D1_coll_mem[7][11]_lut_out, GLOBAL(g_clk), , , D1L212, , );


--D1L21 is mydram:inst2|Mux~303 at LC1_B6
--operation mode is normal