ram_all.v

VERILOG HDL 实际工控项目源码

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// Generated by Quartus II Version 4.1 (Build Build 207 08/26/2004)
// Created on Tue Sep 14 08:02:11 2004

//  Module Declaration
module ram_all
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	din, strb, page, dsp_rw, dsp_a, wr_a, wr_en, d
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input [13:0] din;
	input strb;
	input page;
	input dsp_rw;
	input [2:0] dsp_a;
	input [2:0] wr_a;
	input wr_en;
	inout [13:0] d;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
wire  [3:0]page;	
wire [7:0] rd_addr ,wr_addr;
assign rd_addr[0]=(~strb)&dsp_rw&(~page[3])&(~dsp_a[2])&(~dsp_a[1])&(~dsp_a[0]);
assign rd_addr[1]=(~strb)&dsp_rw&(~page[3])&(~dsp_a[2])&(~dsp_a[1])&dsp_a[0];
assign rd_addr[2]=(~strb)&dsp_rw&(~page[3])&(~dsp_a[2])&dsp_a[1]&(~dsp_a[0]);
assign rd_addr[3]=(~strb)&dsp_rw&(~page[3])&(~dsp_a[2])&dsp_a[1]&dsp_a[0];
assign rd_addr[4]=(~strb)&dsp_rw&(~page[3])&dsp_a[2]&(~dsp_a[1])&(~dsp_a[0]);
assign rd_addr[5]=(~strb)&dsp_rw&(~page[3])&dsp_a[2]&(~dsp_a[1])&dsp_a[0];
assign rd_addr[6]=(~strb)&dsp_rw&(~page[3])&dsp_a[2]&dsp_a[1]&(~dsp_a[0]);
assign rd_addr[7]=(~strb)&dsp_rw&(~page[3])&dsp_a[2]&dsp_a[1]&dsp_a[0];

assign wr_addr[0]=wr_en&(~wr_a[2])&(~wr_a[1])&(~wr_a[0]);
assign wr_addr[1]=wr_en&(~wr_a[2])&(~wr_a[1])&wr_a[0];
assign wr_addr[2]=wr_en&(~wr_a[2])&wr_a[1]&(~wr_a[0]);
assign wr_addr[3]=wr_en&(~wr_a[2])&wr_a[1]&wr_a[0];
assign wr_addr[4]=wr_en&wr_a[2]&(~wr_a[1])&(~wr_a[0]);
assign wr_addr[5]=wr_en&wr_a[2]&(~wr_a[1])&wr_a[0];
assign wr_addr[6]=wr_en&wr_a[2]&wr_a[1]&(~wr_a[0]);
assign wr_addr[7]=wr_en&wr_a[2]&wr_a[1]&wr_a[0];



	
ram m0(	.oe(rd_addr[0]) ,.g(wr_addr[0]) ,.din(din) ,.d(d) );
ram m1(	.oe(rd_addr[1]) ,.g(wr_addr[1]) ,.din(din) ,.d(d) );
ram m2(	.oe(rd_addr[2]) ,.g(wr_addr[2]) ,.din(din) ,.d(d) );
ram m3(	.oe(rd_addr[3]) ,.g(wr_addr[3]) ,.din(din) ,.d(d) );
ram m4(	.oe(rd_addr[4]) ,.g(wr_addr[4]) ,.din(din) ,.d(d) );
ram m5(	.oe(rd_addr[5]) ,.g(wr_addr[5]) ,.din(din) ,.d(d) );
ram m6(	.oe(rd_addr[6]) ,.g(wr_addr[6]) ,.din(din) ,.d(d) );
ram m7(	.oe(rd_addr[7]) ,.g(wr_addr[7]) ,.din(din) ,.d(d) );


endmodule