myfifo.eda.rpt

VERILOG HDL 实际工控项目源码

EDA Netlist Writer report for myfifo
Thu Oct 14 17:17:37 2004
Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Tool Settings
  4. Simulation Tool Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Thu Oct 14 17:17:37 2004 ;
; Revision Name             ; myfifo                                ;
; Top-level Entity Name     ; myfifo                                ;
; Family                    ; FLEX10K                               ;
; Simulation Tool Writer    ; Successful                            ;
+---------------------------+---------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Simulation Tool Settings                                                                             ;
+------------------------------------------------------+-----------------------------------------------+
; Option                                               ; Setting                                       ;
+------------------------------------------------------+-----------------------------------------------+
; Tool Name                                            ; ModelSim (Verilog HDL output from Quartus II) ;
; Generate Netlist for Functional Simulation Only      ; Off                                           ;
; Time scale                                           ; 1 ps                                          ;
; Truncate long hierarchy paths                        ; Off                                           ;
; Map illegal Verilog HDL characters                   ; Off                                           ;
; Flatten buses into individual nodes                  ; Off                                           ;
; Maintain hierarchy                                   ; Off                                           ;
; Bring out device-wide set/reset signals as ports     ; Off                                           ;
; Output Excalibur stripe as a single module or entity ; Off                                           ;
; Generate Power Input File                            ; Off                                           ;
+------------------------------------------------------+-----------------------------------------------+


+---------------------------------------------+
; Simulation Tool Generated Files             ;
+---------------------------------------------+
; Generated Files                             ;
+---------------------------------------------+
; E:/FPGApro/simulation/modelsim/myfifo.vo    ;
; E:/FPGApro/simulation/modelsim/myfifo_v.sdo ;
+---------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version
    Info: Processing started: Thu Oct 14 17:17:35 2004
Info: Command: quartus_eda --import_settings_files=off --export_settings_files=off myfifo -c myfifo
Info: Generated files myfifo.vo and myfifo_v.sdo in directory E:/FPGApro/simulation/modelsim/ for EDA simulation tool
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Oct 14 17:17:37 2004
    Info: Elapsed time: 00:00:01