i2c_slave_model.fdo

来自「i2c code for the verilog」· FDO 代码 · 共 14 行

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sun Aug 01 10:57:30 中国标准时间 2004
##
vlib work
vlog  i2c_slave_model.v
vlog  C:/Program Files/Xilinx/verilog/src/glbl.v
vsim -t 1ps  -L xilinxcorelib_ver -L unisims_ver  -lib work i2c_slave_model glbl
do i2c_slave_model.udo
view wave
add wave *
view structure
view signals
run 1000ns