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FontAngle "normal"
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FontSize 9
FontWeight "normal"
FontAngle "normal"
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System {
Name "complemult"
Location [18, 83, 1003, 701]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType "S-Function"
Name "BusConcatenation"
Ports [2, 1]
Position [590, 131, 695, 184]
ForegroundColor "blue"
AncestorBlock "bus_alteradspbuilder/BusConcatenation"
FunctionName "SBusConcat"
Parameters "-1 bwl bwr blean"
MaskType "Bus Concatenation AlteraBlockSet"
MaskDescription "Bus Concatenation\n\nConcatenates two buses. Th"
"e result is AB, where B is the LSB slice of the output bus, and A is the MSB "
"slice of the output bus.\n"
MaskHelp "web([GetDocAltr(204)])"
MaskPromptString "Bus A Width |Bus B Width |Output"
" is Signed"
MaskStyleString "popup(1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17"
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MaskCallbackString "||"
MaskEnableString "on,on,on"
MaskVisibilityString "on,on,on"
MaskToolTipString "on,on,on"
MaskVarAliasString ",,"
MaskVariables "bwl=@1;bwr=@2;blean=@3;"
MaskInitialization "a = ['a[' num2str(bwl-1) ':0]'];\nb = ['b[' num"
"2str(bwr-1) ':0]'];\nc = ['ab[' num2str(bwr+bwl-1) ':0]'];"
MaskDisplay "plot([0 10 10 10 20], [ 0 0 3 3 3 ])\nplot([0 1"
"0 10 10 20], [ 10 10 7 7 7 ])\nport_label('input',1,a);\nport_label('input',2"
",b);\nport_label('output',1,c);"
MaskIconFrame off
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
MaskValueString "8|8|off"
MaskTabNameString ",,"
}
Block {
BlockType Reference
Name "Complex\nMultiplexer"
Ports [3, 1]
Position [1395, 314, 1440, 366]
ForegroundColor "blue"
SourceBlock "cplx_alteradspbuilder/Complex\nMultiplexer"
SourceType "ComplexMux Altera BlockSet"
}
Block {
BlockType Reference
Name "Complex\nMultiplexer1"
Ports [3, 1]
Position [1245, 269, 1290, 321]
ForegroundColor "blue"
SourceBlock "cplx_alteradspbuilder/Complex\nMultiplexer"
SourceType "ComplexMux Altera BlockSet"
}
Block {
BlockType Reference
Name "Complex\nProduct "
Ports [2, 1]
Position [455, 132, 490, 188]
ForegroundColor "blue"
SourceBlock "cplx_alteradspbuilder/Complex Product "
SourceType "Complex Calc AlteraBlockSet"
direction "Multiply"
}
Block {
BlockType Reference
Name "Complex to\nReal-Imag"
Ports [1, 2]
Position [120, 704, 165, 726]
ForegroundColor "blue"
ShowName off
SourceBlock "cplx_alteradspbuilder/Complex to\nReal-Imag"
SourceType "ComplexTo RealImag Altera BlockSet"
BusType "Signed Integer"
bwl "8"
bwr "0"
}
Block {
BlockType Reference
Name "Constant"
Description "Sign Binary Fractionnal"
Ports [0, 1]
Position [70, 106, 120, 124]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Constant"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Constant"
bwl "32"
bwr "0"
sat off
rnd off
bp off
mask_cst "10"
ncstsamp "1"
cst "10"
modulename "Constant"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Constant1"
Description "Sign Binary Fractionnal"
Ports [0, 1]
Position [70, 216, 120, 234]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Constant"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Constant"
bwl "16"
bwr "0"
sat off
rnd off
bp off
mask_cst "10"
ncstsamp "1"
cst "10"
modulename "Constant"
nSgCpl "0"
}
Block {
BlockType Reference
Name "DataImag"
Ports [1, 1]
Position [275, 126, 350, 144]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConversion"
SourceType "SubBus Altera BlockSet"
Inputs "Signed Integer"
bwl "16"
bwr "0"
Outputs "Signed Integer"
obwl "8"
obwr "0"
msb "15"
lsb "8"
rnd off
sat off
}
Block {
BlockType Reference
Name "DataImag1"
Ports [1, 1]
Position [275, 221, 350, 239]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConversion"
SourceType "SubBus Altera BlockSet"
Inputs "Signed Integer"
bwl "16"
bwr "0"
Outputs "Signed Integer"
obwl "8"
obwr "0"
msb "15"
lsb "8"
rnd off
sat off
}
Block {
BlockType Reference
Name "DataReal"
Ports [1, 1]
Position [275, 81, 350, 99]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConversion"
SourceType "SubBus Altera BlockSet"
Inputs "Signed Integer"
bwl "16"
bwr "0"
Outputs "Signed Integer"
obwl "8"
obwr "0"
msb "7"
lsb "0"
rnd off
sat off
}
Block {
BlockType Reference
Name "DataReal1"
Ports [1, 1]
Position [275, 176, 350, 194]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConversion"
SourceType "SubBus Altera BlockSet"
Inputs "Signed Integer"
bwl "16"
bwr "0"
Outputs "Signed Integer"
obwl "8"
obwr "0"
msb "7"
lsb "0"
rnd off
sat off
}
Block {
BlockType Reference
Name "Dataa\nto Complex"
Ports [2, 1]
Position [375, 104, 410, 146]
ForegroundColor "blue"
SourceBlock "cplx_alteradspbuilder/Real-Imag \nto Complex"
SourceType "RealImagToComplex AlteraBlockSet"
BusType "Signed Integer"
bwl "16"
bwr "0"
}
Block {
BlockType Reference
Name "Datav\nto Complex"
Ports [2, 1]
Position [375, 194, 410, 236]
ForegroundColor "blue"
SourceBlock "cplx_alteradspbuilder/Real-Imag \nto Complex"
SourceType "RealImagToComplex AlteraBlockSet"
BusType "Signed Integer"
bwl "16"
bwr "0"
}
Block {
BlockType Reference
Name "Input"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [155, 217, 220, 233]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "16"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input1"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [160, 107, 225, 123]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "16"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input1"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Real\nResult"
Ports [1, 2]
Position [525, 134, 560, 181]
ForegroundColor "blue"
SourceBlock "cplx_alteradspbuilder/Complex to\nReal-Imag"
SourceType "ComplexTo RealImag Altera BlockSet"
BusType "Signed Integer"
bwl "8"
bwr "0"
}
Block {
BlockType Reference
Name "Result1"
Ports [1, 1]
Position [720, 149, 790, 171]
ForegroundColor "blue"
SourceBlock "sopc_alteradspbuilder/Custom Instruction/Result"
"1"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Output Port"
bwl "32"
bwr "0"
sat off
rnd off
bp off
cst "0"
LocPin "SOPC_CI_RESULT"
modulename "Result1"
ppat "c:\\temp"
nSgCpl "0"
}
Block {
BlockType Scope
Name "Scope"
Ports [2]
Position [850, 131, 880, 164]
Floating off
Location [188, 365, 512, 604]
Open off
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "-5~-5"
YMax "5~5"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [189, 348, 258, 395]
ForegroundColor "blue"
SourceBlock "ALTELINK/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "Stratix"
opt "Speed"
synthtool "Others"
vstim on
SynthAct "None"
workdir "I:\\PGC\\dspbuild\\200651000346-99\\comple_mult"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation off
JTAGCable "USB-Blaster [USB-0]"
}
Line {
SrcBlock "Dataa\nto Complex"
SrcPort 1
Points [15, 0; 0, 20]
DstBlock "Complex\nProduct "
DstPort 1
}
Line {
SrcBlock "Datav\nto Complex"
SrcPort 1
Points [20, 0; 0, -40]
DstBlock "Complex\nProduct "
DstPort 2
}
Line {
SrcBlock "Complex\nProduct "
SrcPort 1
DstBlock "Real\nResult"
DstPort 1
}
Line {
SrcBlock "BusConcatenation"
SrcPort 1
DstBlock "Result1"
DstPort 1
}
Line {
SrcBlock "Real\nResult"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "BusConcatenation"
DstPort 1
}
Branch {
Points [0, -50; 265, 0]
DstBlock "Scope"
DstPort 1
}
}
Line {
SrcBlock "Real\nResult"
SrcPort 2
Points [5, 0]
Branch {
DstBlock "BusConcatenation"
DstPort 2
}
Branch {
Points [0, 55; 265, 0]
DstBlock "Scope"
DstPort 2
}
}
Line {
SrcBlock "Input"
SrcPort 1
Points [20, 0]
Branch {
Points [15, 0]
DstBlock "DataImag1"
DstPort 1
}
Branch {
Points [0, -40]
DstBlock "DataReal1"
DstPort 1
}
}
Line {
SrcBlock "DataImag"
SrcPort 1
DstBlock "Dataa\nto Complex"
DstPort 2
}
Line {
SrcBlock "Input1"
SrcPort 1
Points [30, 0]
Branch {
Points [0, 0]
DstBlock "DataImag"
DstPort 1
}
Branch {
DstBlock "DataReal"
DstPort 1
}
}
Line {
SrcBlock "DataReal"
SrcPort 1
Points [0, 25]
DstBlock "Dataa\nto Complex"
DstPort 1
}
Line {
SrcBlock "Constant1"
SrcPort 1
DstBlock "Input"
DstPort 1
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "Input1"
DstPort 1
}
Line {
SrcBlock "DataReal1"
SrcPort 1
Points [0, 20]
DstBlock "Datav\nto Complex"
DstPort 1
}
Line {
SrcBlock "DataImag1"
SrcPort 1
Points [0, -5]
DstBlock "Datav\nto Complex"
DstPort 2
}
}
}
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