complemultaltblk.xml

matlab下

            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>2</dstport>
            <dstblk>DatavtoComplex</dstblk>
         </port_db>
         <nparameter>11</nparameter>
      </db_block>
      <db_block>
         <instancename>DataReal</instancename>
         <sourcename>SubBusAlteraBlockSet</sourcename>
         <instancenumber>9</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
            <pname>BusType</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>Outputs</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>16</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>obwl</pname>
            <pvalue>8</pvalue>
            <pname>obwr</pname>
            <pvalue>0</pvalue>
            <pname>lsb</pname>
            <pvalue>0</pvalue>
            <pname>msb</pname>
            <pvalue>7</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Input1</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>DataatoComplex</dstblk>
         </port_db>
         <nparameter>11</nparameter>
      </db_block>
      <db_block>
         <instancename>DataReal1</instancename>
         <sourcename>SubBusAlteraBlockSet</sourcename>
         <instancenumber>10</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
            <pname>BusType</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>Outputs</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>16</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>obwl</pname>
            <pvalue>8</pvalue>
            <pname>obwr</pname>
            <pvalue>0</pvalue>
            <pname>lsb</pname>
            <pvalue>0</pvalue>
            <pname>msb</pname>
            <pvalue>7</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Input</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>DatavtoComplex</dstblk>
         </port_db>
         <nparameter>11</nparameter>
      </db_block>
      <db_block>
         <instancename>DataatoComplex</instancename>
         <sourcename>RealImagToComplexAlteraBlockSet</sourcename>
         <instancenumber>11</instancenumber>
         <inport>2</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
            <pname>BusType</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>16</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>DataReal</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>DataImag</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>ComplexProduct</dstblk>
         </port_db>
         <nparameter>4</nparameter>
      </db_block>
      <db_block>
         <instancename>DatavtoComplex</instancename>
         <sourcename>RealImagToComplexAlteraBlockSet</sourcename>
         <instancenumber>12</instancenumber>
         <inport>2</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
            <pname>BusType</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>16</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>DataReal1</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>DataImag1</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>2</dstport>
            <dstblk>ComplexProduct</dstblk>
         </port_db>
         <nparameter>4</nparameter>
      </db_block>
      <db_block>
         <instancename>ComplextoRealImag</instancename>
         <sourcename>ComplexToRealImagAlteraBlockSet</sourcename>
         <instancenumber>13</instancenumber>
         <inport>1</inport>
         <outport>2</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>BusType</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>8</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>4</nparameter>
      </db_block>
      <db_block>
         <instancename>RealResult</instancename>
         <sourcename>ComplexToRealImagAlteraBlockSet</sourcename>
         <instancenumber>14</instancenumber>
         <inport>1</inport>
         <outport>2</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
            <pname>BusType</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>8</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>ComplexProduct</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>2</outportfanout>
            <dstport>1</dstport>
            <dstblk>BusConcatenation</dstblk>
            <outportpos>2</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>2</outportfanout>
            <dstport>2</dstport>
            <dstblk>BusConcatenation</dstblk>
         </port_db>
         <nparameter>4</nparameter>
      </db_block>
      <db_block>
         <instancename>ComplexProduct</instancename>
         <sourcename>ComplexCalcAlteraBlockSet</sourcename>
         <instancenumber>15</instancenumber>
         <inport>2</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
            <pname>direction</pname>
            <pvalue>Multiply</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>DataatoComplex</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>DatavtoComplex</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>RealResult</dstblk>
         </port_db>
         <nparameter>2</nparameter>
      </db_block>
      <db_block>
         <instancename>ComplexMultiplexer</instancename>
         <sourcename>ComplexMuxAlteraBlockSet</sourcename>
         <instancenumber>16</instancenumber>
         <inport>3</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>1</nparameter>
      </db_block>
      <db_block>
         <instancename>ComplexMultiplexer1</instancename>
         <sourcename>ComplexMuxAlteraBlockSet</sourcename>
         <instancenumber>17</instancenumber>
         <inport>3</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>1000000000000</pvalue>
         </parameters_db>
         <port_db>
         </port_db>
         <nparameter>1</nparameter>
      </db_block>
   </block_dspbuilder>
<top_sources>
	<library></library>
</top_sources>
   <top_parameters>
      <starttime>0.0</starttime>
      <stoptime>10</stoptime>
      <fixedstep>auto</fixedstep>
      <nsubsystem>0</nsubsystem>
      <nblocks>17</nblocks>
   </top_parameters>
   <top_signalcompiler>
      <family>Stratix</family>
      <opt>Speed</opt>
      <synthtool>Others</synthtool>
      <vstim>on</vstim>
      <SynthAct>None</SynthAct>
      <workdir>E:\sunyu\PGC\dspbuild\200651000346-99\comple_mult</workdir>
      <Procetype>prod</Procetype>
      <UseReset>on</UseReset>
      <ResetPin>Active High</ResetPin>
      <ClockPin>Output to Pin</ClockPin>
      <ClockPeriod>20</ClockPeriod>
      <UseSignalTap>off</UseSignalTap>
      <CreatePtfFile>off</CreatePtfFile>
      <SignalTapDepth>128</SignalTapDepth>
      <VerilogSupport>off</VerilogSupport>
      <JTAGCable>USB-Blaster [USB-0]</JTAGCable>
      <bContainMegaCoreIpTb>0</bContainMegaCoreIpTb>
   </top_signalcompiler>
</complemult>